In the framework of the project “Absolute interferometry for stellar interferometers” supported by theswiss national funds FINES, we are currently developing an “Optical Phase Detection Unit” (OPDU) forthe PRIMA facility of the Very Large Telescope Interferometer. The concept of this OPDU has alreadybeen established during a rider study on the PRIMA metrology supported by ESO [AD1] and a prototypeversion has been built. In this report, we propose a more detailed design of the final version of the OPDUand we present some experimental tests in order to verify its performance.
2 Applicable documents
[AD1] Prima Metrology Rider Study, VLT-TRE-IMT-15700-0001, 7/3/00.[AD2] Technical Specification for the PRIMA Metrology System, VLT-SPE-ESO-15730-2211, Is-
sue 1.0, 16/10/00.[AD3] Optical Phase Detector Unit for the PRIMA Metrology System, Design Review, VLT-TRE-
IMT-15734-0002, 20/11/00.[AD4] Technical Specification for the Design of the Phase Meter of the PRIMA Metrology System,
VLT-SPE-ESO-15734-2921, Issue 1.0, 5/12/02.
3 Acronyms
EOB End Of Block
EOT End Of Text
LCU Local Control Unit
NEP Noise Equivalent Power
OPD Optical Path Difference
OPDU Optical Phase Detection Unit
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PLD Programmable Logic Device
PLL Phase-Locked Loop
SNR Signal to Noise Ratio
SOB Start Of Block
SOT Start Of Text
TIM Time Interface Module
VCO Voltage Controlled Oscillator
4 Principle
The setup of Fig. 1 is composed of two heterodyne interferometers, one for the reference object, with aheterodyne frequency of 650 kHz and the other for the science object, with a heterodyne frequency of450 kHz. A Nd:YAG laser emitting at 1319 nm will be used for both interferometers. The wavelength of1319 nm was chosen to avoid straylight affecting the wavefront curvature sensor of the adaptive opticssystem that works in the visible spectrum.
In the phasemeter prototype, a frequency offset of 80 MHz was generated between both interferometersto avoid crosstalk. The heterodyne frequencies were generated using acousto-optic modulators workingat +40 and+39.35MHz for the reference interferometer and at−40 and−39.55MHz for the scienceinterferometer. However, it was discovered that the acousto-optic modulators suffer from acoustic backreflections in the crystal. As a result, the device optimized for+40MHz frequency shift also exhibits asmall amount of optical power which is down shifted by 40MHz. This behaviour led to parasitic super-heterodyne signals at 200 kHz that affected the phase resolution. Therefore, for the remaining of the tests,the operating frequency of the acousto-optic modulators generating the 650 kHz signal were changed to38 and 38.65 MHz. The frequency offset between both interferometers is therefore of 78 MHz. Table 1lists the frequencies used in the final version of the phasemeter.
Channel A (science) Channel B (ref)
ν+38MHz ν+38.65MHz ν−39.55MHz ν−40MHz
f1 = 650kHz f2 = 450kHz
ν = 3×108/1319×10−9Hz
∆ν = 78MHz
f1− f2 = 200kHz
Table 1: Heterodyne frequencies for reference and science interferometers.
After AC coupling, the two detected interference signals are of the form
Imeas,1 = I1cos(2πf1t+ϕ1) and Imeas,2 = I2cos(2πf2t+ϕ2) (1)
with
ϕ1 =4πν
cL1 and ϕ2 =
4π(ν+∆ν)c
L2 (2)
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DL DD
LI 2
Tele
scop
e 1
Tele
scop
e 2
Freq
uenc
y sh
ifter
m
odul
e
Seco
ndar
y FS
U
LASE
RFr
eque
ncy
shift
er
mod
ule
I 1
Ref
eren
ce o
bjec
t
Scie
nce
obje
ct
PRIM
ARY
FSU
Ret
rore
flect
or o
n M
2
Figure 1: Principle of detection.
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where L1, L2 are the path difference for the science and reference interferometers, respectively.
The optical phase detection unit (OPDU) is shown in Fig. 2. It consists of four photodetectors, twosuperheterodyne modules and a digital phasemeter.
450 kHzSuperheterodyne module Phasemeter,
Phase errorcompensation
Photodetectors
Superheterodyne module
200 kHz
200 kHz
Mixer
Mixer
Imeas,1
650 kHz
Imeas,2
450 kHz
Iref,1
650 kHz
Iref,2
Limiter
Limiter
Limiter
Limiter
Limiter
Limiter
DigitalPhasemeter
ErrorcompensationFringe counter
Figure 2: Optical phase detection unit.
4.1 Photodetectors
The four InGaAs photodetectors measure the two probe signals Imeas,1 and Imeas,2 for the science andreference interferometers respectively, and their corresponding reference signals Iref,1 and Iref,2. Weshowed in [AD1] that the minimal optical power which is required to achieve the desired resolution islimited by the electronic noise (amplifier noise + thermal noise). Therefore, the photodetectors shouldbe designed to achieve the best signal-to-noise ratio (SNR).
4.2 Superheterodyne modules
The superheterodyne module allows to access directly the difference of the interferometric phasesϕ1−ϕ2
which is mainly sensitive to the differential optical path difference∆L = L1− L2. Indeed, by mixingelectronically the two interference signals and by band-pass filtering around f1− f2, we obtain a signal
Imeas(t) = I12cos[2π(f1− f2)t+ϕ1−ϕ2] . (3)
Similarly, a reference signal of frequency f1− f2 is generated from the two individual reference signals re-lated to each interferometer by means of the second superheterodyne module. Each module is composedof input bandpass filters around f1 and f2 to suppress the possible crosstalks between each channel, anelectronic mixer, and an output bandpass filter around f1− f2. The bandwidth of the filters should allowto monitor the OPD variations of L1 and L2 imposed by the delay lines, the variable curvature mirror,and the differential delay line. The two heterodyne frequencies must be chosen separated enough tosuppress at the most the possible cross-talks. We selected therefore in [AD1] heterodyne frequencies off1 = 650kHz and f2 = 450kHz.
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4.3 Phasemeter
The phaseϕ1−ϕ2 is then measured with a custom designed phasemeter. The sinusoidal reference andprobe signals are first converted to square signals by means of limiting amplifiers. Then, the signalsare fed to a digital zero-crossing phasemeter. The time interval between leading edges of the referenceand probe signals is measured by means of binary counter and an internal clock. To avoid any driftbetween the superheterodyne frequency f1− f2 and the internal clock frequency fc, the internal clock isobtained from a phase-locked loop which multiplies the frequency f1− f2 by a factor of 1024, leading toa resolution of 2π/1024.
The phasemeter is combined with an optical fringe counter to achieve a very large dynamic range. Aninteger and fractional fringe number i and f is thus provided. These values can be accumulated over auser-defined integration time T by means of digital adders to average out some high frequency metrologyerrors.
4.4 Phase error compensation
The phase difference is rigorously given by
ϕ1−ϕ2 =4πν
c∆L− 4π∆ν
cL2. (4)
As already mentioned, the first term depends only on the differential optical path difference. However,the second term is sensitive to the individual optical path difference L2 of the reference interferometer.Since∆ν is small compared to the optical frequencyν, the phase difference is not very sensitive to L2.However, since the delay line can move over several meters during the observation, we have to takethis phase variation into account. The variation of L2 will therefore be estimated using the individualinterference signal I2(t) and its corresponding reference signal at frequency f2. It has been shown that asimple fringe counter is amply sufficient to compensate this error.
5 Design of the photodetectors
A typical photodetector circuit is depicted in Fig. 3. The resistor R fixes the transimpedance gain in V/A.Several sources of noise are inherent in the process of photodetection. The main contributions are: Shotnoise (i), Johnson noise (ii), and amplifier noise (iii). The performance of a photodetector is usuallycharacterized by its Noise Equivalent Power (NEP). For a Johnson noise limited detection, the NEP isgiven by
NEP=√
4kB T RR S1.3µm
(5)
where kB is the Boltzmann constant, T is the temperature and S is the sensitivity of InGaAs at 1.3µmin A/W. The spectral sensitivity of the photodiode is S= ηe/hν, where e is the electron charge,η is thequantum efficiency of the detector, andν the optical frequency. Since the quantum efficiency of InGaAsat 1.3µm is typically 0.8, the sensitivity at 1.3µm is about 0.88 A/W.
The photodiode is an InGaAs photodiode in FC receptacle (FD100FC), commercially available fromFermionics (CA), with a diameter of 100µm, a spectral sensitivity of 0.88 A/W at 1.3µm, a dark currentof max. 0.15 nA and a terminal capacitance of less than 1 pF.
OS, 28.8.2003 Institute of Microtechnology, Neuchâtel
The design of the transimpedance circuit is based on an application note of Siliconix [AD3]. The op-erational amplifier consists of a discrete FET differential preamplifier followed by a monolithic bipolaroperational amplifier. This allows to use a relatively high bandwidth for a high transimpedance gain(1.4MΩ). Low-noise electronic components have been selected for optimal performance.
The photodetector has a bandwidth of 7.5 MHz and a noise level at 650 kHz of about -128 dBm/Hz(electrical power in 50Ω), corresponding to a noise equivalent power of about 0.14pW/
√Hz. This
value is very close to the Johnson noise limit at 300 K (0.12pW/√
Hz).
Table 2 summarizes the specifications of the photodetectors.
6 Design of the superheterodyne module
450 kHz
200 kHz
200 kHz
Mixer
Mixer
Imeas,1
650 kHz
Imeas,2
450 kHz
Iref,1
650 kHz
PreampFilter Limiter Mixer
Iref,2
Limiter
Limiter
Limiter
Limiter
Limiter
Limiter
Figure 4: Global design of the superheterodyne module.
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Photodiode 100µm InGaAs pigtailed
Response 800–1800 nm
Transimpedance gain 1.4×106V/A
Bandwidth DC to 7.5 MHz
Sensitivity 1.2V/µW
Output impedance 50Ω
Output voltage (50Ω) 0–1.7 V
Output voltage (Hi-Z) 0–3.4 V
Saturation level 1.4µW
Offset Adjustable
Noise (typical) from 10 Hz to 800 kHz -128 dBm/Hz
Noise (max) at 6 MHz -115 dBm/Hz
NEP at 1300 nm 0.14pW/√
Hz
Table 2: Summary of the photodetector specifications.
Figure 4 shows the global design of the superheterodyne module.
The superheterodyne module is composed of three boards:
• Photodetectors, preamplifiers and bandpass filters (PreampFilter);
• Limiting amplifiers (Limiter);
• Mixers (Mixer).
All boards use the±12V supply voltage available on the P1 connector of the VME crate. In orderto protect from the parasitic frequencies of the power supply, all the operational amplifiers used in thephasemeter are equipped with a low-pass filter on the +12 V and -12 V power supply lines. These RCfilters, with a bandwidth of around 3.2 kHz, reduce the parasitic frequencies of the switching powersupply (typically ranging from 150 to 800 kHz) with an attenuation better than 34 dB.
On the front panels, the inputs are SM-A connectors and the outputs are LEMO CAMAC unipolar Series00 connectors.
6.1 Preamplifiers and filters
After detection, the four signals are filtered using bandpass filters at 450 and 650 kHz. The preamplifiersconsist of one amplifiers at the input of the filter and one at the output. This configuration ensures inputand output impedances of 50Ω for the filters and thus prevent problems due to impedance mismatchbetween the different building blocks of the superheterodyne module. The gain of the input and outputamplifiers is of 23.6 dB and 11.6 dB, respectively.
The electronic circuits of the filters (tenth order Chebyshev filters) are shown in Annex B. Because of themovement of the delay lines, the heterodyne frequencies may vary from 425 kHz to 475 kHz and from
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625 kHz to 675 kHz. The bandwidth of the filters must therefore be wide enough to pass these rangesof frequencies. According to the specification [AD4], the bandwidth will be of 110 kHz (±55kHz)for the input filters and of 55 kHz (±27.5kHz) for the output filters. It is also important for the phaseresponse of a pair of filters (one filter at 450 kHz and one at 650 kHz) to be as identical as possibleover their bandwidth in order to minimize the phase shifts introduced by the variation of the heterodynefrequencies during delay lines movement. Therefore, all the selfs in the filters are tunable, making itpossible to match the phase response of each pair of filters.
For testing purposes, it is possible to unplug the photodetectors and enter an electric signal on the boardinstead. The input will have to be switched manually by unplugging the photodetector cable on theboard and plugging the electrical input instead (dashed line in Annex A). A parking connector will beavailable on the board to secure the unused cable. This mechanism was chosen instead of a relay becauseof the bandwidth limitation of standard relay components. The electrical inputs will be protected fora maximum voltage of 15 Vpp using diodes. In addition, the photodetector output (DC coupled) isavailable on the front panel for monitoring.
The DC level of the photodetector is made available after a lowpass filter to be digitized on the digitalphase meter board (see 7.6).
Table 3 lists the input and outputs of the PreampFilter board.
6.2 Limiting amplifiers
The filtered heterodyne signals are converted to square signals using a limiter stage before the mixerstage. There are two benefits to using square signals:
• The mixing efficiency is higher compared to sinusoidal signals;
• The mixing efficiency depends on the amplitude of the input signals. A square signal of constantamplitude at the input of the mixer board makes it possible to adjust the amplitude of the signalsfor maximum efficiency using an amplifier with a variable gain at the mixer input.
The limiting amplifier is composed of two stages. The first stage amplifies the signal with a high gainand limits the amplitude using diodes. The second stage is a comparator that delivers a square signal inTTL format.
The 450 kHz reference and probe signals are also provided on a second output for the error compensationfringe counter on the digital phasemeter board.
Another signal is generated on this board and will be used to provide status information on the hetero-dyne frequencies (see 7.6). A buffer with a high input impedance is used to take a part of the input signal.A window comparator then converts the signal into a square signal that will be used for frequency mea-surement on the digital board and also introduces a threshold voltage under which the it gives no output,meaning that the amplitude of the heterodyne signal is too low. The threshold voltage will be adjustable.
Table 4 lists the input and outputs of the Limiter board. The electronic circuits are shown in Annex C.
6.3 Mixers
At each input of the mixer, an AC amplifier with an adjustable gain is used to remove the DC componentof the input TTL signal and adjust its amplitude for maximum mixing efficiency. The gain is adjustedusing a potentiometer located on the board.
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Input Description Location Connector
Ref
INOPT1 Optical input for the 450 kHz reference signal Front SM-A
INOPT2 Optical input for the 650 kHz reference signal ” SM-A
INEL1 Electrical input for the 450 kHz reference signal ” SM-A
INEL2 Electrical input for the 650 kHz reference signal ” SM-A
Probe
INOPT1 Optical input for the 450 kHz probe signal Front SM-A
INOPT2 Optical input for the 650 kHz probe signal ” SM-A
INEL1 Electrical input for the 450 kHz probe signal ” SM-A
INEL2 Electrical input for the 650 kHz probe signal ” SM-A
Electrical inputs Nominal value 3 dBm (0.9Vpp)
Maximal value 8 dBm (1.6Vpp)
Destruction value 27 dBm (15Vpp)
Output Description Location Connector
Ref
OUT 450kHz 450 kHz filtered reference signal Front LEMO
OUT 650kHz 650 kHz filtered reference signal ” LEMO
DET1 OUT Photodetector output of the 450 kHz reference signal ” LEMO
DET2 OUT Photodetector output of the 650 kHz reference signal ” LEMO
DC REF 450kHz DC level of the 450 kHz reference signal Back (P2) DIN 41612
DC REF 650kHz DC level of the 650 kHz reference signal ” DIN 41612
Probe
OUT 450kHz 450 kHz filtered probe signal Front LEMO
OUT 650kHz 650 kHz filtered probe signal ” LEMO
DET1 OUT Photodetector output of the 450 kHz probe signal ” LEMO
DET2 OUT Photodetector output of the 650 kHz probe signal ” LEMO
DC PROBE 450kHz DC level of the 450 kHz probe signal Back (P2) DIN 41612
DC2 PROBE 650kHz DC level of the 650 kHz probe signal ” DIN 41612
Table 3: Input and outputs of the preamplifiers and filters board. SM-A: SM-A female; LEMO: LEMOCAMAC unipolar series 00; DIN 41612: DIN 41612 3×32 male.
In the prototype version of the phasemeter, there was an impedance mismatch between the output of themixer and the input of the 200 kHz filter. Indeed, the input impedance of the filter was of 50Ω for a200 kHz signal, but increased as the frequency differed from the bandpass frequency. In consequence,the frequencies of 450, 650 and 1100 kHz at the output of the mixer (remains of the input signals and sumof the frequencies) were reflected back into the latter and mixed again with the other signals, generatingadditional, parasitic components with a frequency of 200 kHz.
To work around this problem, buffers were added to the filters input and output in order to match theimpedance to 50Ω for all the frequencies. Moreover, in order to simplify their design, the same schematicwas used for all the bandpass filters. Therefore, the preamplifiers needed on the 450 and 650 kHz chan-nels were implemented as input and output buffers, splitting the gain between both stages, as describedearlier.
The output of the mixer is filtered at 200 kHz with a bandwidth of 55 kHz. The design of the 200 kHzfilter is the same as the 450 and 650 kHz filters, with amplifiers at the input and output that ensure a
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Input Description Location Connector
RefA IN 450kHz 450 kHz filtered reference signal Front SM-A
A IN 650kHz 650 kHz filtered reference signal ” SM-A
ProbeA IN 450kHz 450 kHz filtered probe signal Front SM-A
A IN 650kHz 650 kHz filtered probe signal ” SM-A
Only use the output signals from the preamplifiers and filters board as inputs
Output Description Location Connector
Ref
D OUT 450kHz 450 kHz digital reference signal Front LEMO
D OUT 650kHz 650 kHz digital reference signal ” LEMO
FC OUT 450 kHz digital reference signal for fringe counter ” LEMO
MESR 450kHz 450 kHz reference output for frequency measurement Back (P2) DIN 41612
MESR 650kHz 650 kHz reference output for frequency measurement ” DIN 41612
Probe
D OUT 450kHz 450 kHz digital probe signal Front LEMO
D OUT 650kHz 650 kHz digital probe signal ” LEMO
FC OUT 450 kHz digital probe signal for fringe counter ” LEMO
MESP 450kHz 450 kHz probe output for frequency measurement Back (P2) DIN 41612
MESP 650kHz 650 kHz probe output for frequency measurement ” DIN 41612
Table 4: Input and outputs of the limiting amplifiers board. SM-A: SM-A female; LEMO: LEMOCAMAC unipolar series 00; DIN 41612: DIN 41612 3×32 male.
proper impedance matching and amplify the signal before conversion to the TTL format. Since themixer is working at constant amplitude, the amplification on final limiter stage can be reduced comparedto the prototype, where the large range of input amplitudes required several amplificating stages on thelimiter before the comparator.
Table 5 lists the input and outputs of the Mixer board. The electronic circuits are shown in Annex D.
7 Design of the digital phasemeter
The digital phasemeter is composed of 6 subsystems:
1. Phase-locked loop
2. Phase shifter
3. Digital zero-crossing phasemeter
4. Phase adder
5. Error compensation fringe counter
6. Status registers
A schematic of the digital phasemeter is shown in Annex E.
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Input Description Location Connector
RefD IN 450kHz 450 kHz digital reference signal Front SM-A
D IN 650kHz 650 kHz digital reference signal ” SM-A
RefD IN 450kHz 450 kHz digital probe signal Front SM-A
D IN 650kHz 650 kHz digital probe signal ” SM-A
Only use the output signals from the limiting amplifiers board as inputs
Output Description Location Connector
Ref D OUT 200kHz 200 kHz digital reference signal Front LEMO
Probe D OUT 200kHz 200 kHz digital probe signal Front LEMO
Table 5: Input and outputs of the mixers board. SM-A: SM-A female; LEMO: LEMO CAMAC unipolarseries 00.
7.1 Phase-locked loop
The phase-locked loop is composed of a high-frequency voltage-controlled oscillator (200 MHz) and aphase comparator circuit. The VCO frequency is first divided by 1024 to obtain a signal of roughly200 kHz. An Altera PLD is used for this purpose. The phase of the frequency divided signal is thencompared to the phase of the reference signal of 200 kHz frequency. The output of the phase comparatoris low-pass filtered by a simple RC filter (about 1 MHz cut-off frequency) and then fed back to the VCO.In the phasemeter prototype, the circuit showed a phase jitter of only a few ns.
7.2 Phase shifter
The phase shifter module is used to a reference signal shifted byπ/2 in order to solve the problemencountered with phase values close to zero. It is described in [AD3]. At each raising edge of thereference signal, the counter is enabled. After 256 counts, a pulse is generated, leading to a signal(RefQ) phase shifted byπ/2 relative to the reference signal, assuming the ratio between the clock andreference frequencies is of 1024.
7.3 Digital zero-crossing phasemeter
The principle of the digital zero-crossing phasemeter is described in [AD1]. The design is based on thedesign of the phasemeter prototype, described in [AD3].
When the raising edge of the reference is detected, a 10-bit counter is started. When the raising edge ofthe probe signal is detected, the counter is stopped and the value latched. The same process is applied ina second channel, identical to the first one except that it uses the second reference signal, shifted byπ/2.A multiplexer is used to select the value used for the output, based on the value of the first channel.
A third counter is used to count the number of 2π phase cycles. To monitor a distance of 120 mm, a18-bit counter should be sufficient. For safety, a 19-bit counter was implemented. The total width of theinstantaneous phase is therefore 29 bits.
For testing purpose, the instantaneous phase will be provided on the front panel, using a AMP 2-174225-5 type connector. The pinout corresponds to the National Instruments PCI DIO/32 H digital I/O boardand is presented in annex. The output frequency will be of 200 kHz.
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7.4 Phase adder
In the phasemeter prototype, an on-board averaging function was implemented in programmable logic.In order to simplify the calculations, the averaging could be performed over a number of samples thatwas a power of 2, between 4 and 131072.
In the final version of the phasemeter, it is desired to be able to average data on an arbitrary numberof samples between 25 and 400000, corresponding to an output data rate between 0.5 Hz and 8 kHz.Therefore, the phase adder module performs the sum of the instantaneous phase between two triggersignals from the TIM. This sum and the number of samples summed will be transferred to the LCU,which will perform the division to obtain the average value. The width of the sum is of 48 bits.
The concept of the phase adder is shown in fig. 5. Between two consecutive trigger signals, the instan-taneous phase (IP[0..28]) coming from the instantaneous phasemeter is added by means of a full adder.Simultaneously, a classical counter counts the number of “REQ” signals coming from the instantaneousphasemeter (The REQ signal is active as soon as the output value of the instantaneous phasemeter isupdated). The reset signal allows to reset the full adder and the counter. The output of the full adder issplit in two 32-bit words. The output length of the counter is also of 32 bits. The three 32-bit words feedthen a bus multiplexer, which is driven by two address bits A0 and A1. Depending on the values of A0and A1, one of the three words is selected by the bus multiplexer. An output enable signal (OE) is thenused to drive the output Q[0..32] to the data bus of the phasemeter board.
Full adder
Busmulti-plexer
Counter
OE
A0A1
IP[0..28]
TRIG
REQ
CLK
AP[0..63]
N[0..31]
RESET
Q[0..31]
AP[0..31]
AP[32..63]
Start/stop
Start/stop
Figure 5: Concept of the phase adder.
7.5 Error compensation fringe counter
The principle of the error compensation fringe counter is described in [AD1]. The design is described in[AD3].
The error compensation fringe counter is based on an up/down counter. The output value is incremented
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by the reference signal and decremented by the probe signal. Since the delay lines may travel over severalmeters, a 24-bit output is required. This allows to measure a maximal displacement of 224×660nm=11m.
7.6 Status registers
Status of interferometric signals
The frequency of the four heterodyne signals will be measured using PIC12 microcontrollers (Microchip,USA). These microcontrollers feature an internal 4 MHz clock, an 8-bit real time counter and an 8-bitprescaler. The input frequency is divided by 16 and gated for a duration of 5 ms. The frequency can becalculated with an accuracy of 3.2 kHz from the value of the counter at the end of the measurement. Theoutput is set to 1 if the frequency is within the accepted range, 0 otherwise. The microcontrollers will beprogrammed in assembly language on PROM devices, therefore requiring no maintenance.
The status of the reference 200 kHz signal is determined from the PLL locked output of the PLL circuit.The status of the probe 200 kHz signal is determined in the phase shifter module using a circuit based onthe principle of the watchdog timer. The value of a flip-flop is set by the raising edge of the probe signaland reset by a clock of lower frequency. As long as the probe signal is present, the output is 1. When theprobe signal is absent, the output falls to 0.
Signal level of the photodetectors
The DC level of each photodetector, obtained from the preamplifiers and filters board, will be digitizedover 8 bits. The analog to digital conversion will be performed using four 8-bit, one channel digital toanalog converters (Maxim Integrated Products MAX152 or similar) with a voltage reference of 1.8 Vprovided by an external voltage reference (Maxim Integrated Products MAX6100 or similar). Therefore,the resolution on the DC level of the photodetector will be of 1LSB= 7mV, corresponding to an opticalpower of 5.7 nW.
Other status signals
The other status bits provided are:
• Overflow of the instantaneous phase counter
• Overflow of the error compensation fringe counter
• Trigger detected
• Reset detected
All the status signals are collected into two 32-bit buffers in the format shown of fig. 6.
7.7 Data transfer
There are four different values that must be transferred between the phasemeter and the LCU:
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1. Summed phase (1LSB= 2π/1024rad)
2. Error compensation (1LSB= 0.66µm)
3. Number of samples
4. Status
The data will be transmitted over 6 packets of 32 bits using the format shown of fig. 6. Figure 7 showsthe timing diagram of the data transfer.
The packet counter is a 4-bit counter that is incremented for each packet. It is present in the first andlast data words. Block integrity and sequentiality checks are performed on the Start Of Block (SOB) andEnd Of Block (EOB) bytes, the first and last byte of the packet, respectively:
The six 32-bit words will be made available sequentially on a 32-bit bus. A strobe signal will be issuedwhen each word is ready. The data will be read on the LCU using a PMC-HPDI32 digital IO card. Thesignals will be converted to RS422/485 format using differential line drivers and made available on aconnector of type Robinson Nugent #P50E-080-S-TG on the back side of the P2 backplane. Two LEMOSeries 00 connectors next to it will receive the trigger and reset signals from the TIM.
Table 6 lists the input and outputs of the Phasemeter board and table 7 summarizes the units used.
8 Design summary
The OPDU will be manufactured on four 6HE VME boards, to comply with ESO standards. Thephasemeter will consist of 4 VME boards. The first one will be devoted to the phototdetectors andinput bandpass filters, the second one will contain the limiting amplifiers, the third one will contain themixers and output bandpass filters and the last one will be dedicated to the digital phasemeter, the errorcompensation fringe counter and the interface with the LCU. Each board will have extraction handles.The front panel cables will be labelled to facilitate the cabling of the phasemeter. The sketch of thecomplete phasemeter is shown in Annex A, the schematics of the boards are shown in Annexes B-E andthe layouts of the front panel and backplane are shown in Annexes F and G.
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33
931313131
5047
23
18
33M
SB31
00
2219
48
70
70
70
70
09
87
65
43
21
0 000032LSB 0
024
028
SOT
DC
Ref
450
kD
C P
rob
e 45
0kD
C R
ef 6
50k
DC
Pro
be
650k
Pack
et #
Pack
et #
EOT
Zer
o p
add
ing
(5 b
its)
Zer
o p
add
ing
(14
bit
s)
Phas
e su
m
Phas
e su
m
Nu
mb
er o
f sam
ple
s
Erro
r co
mp
ensa
tio
n
Stat
us
I
Stat
us
I
Stat
us
II
Stat
us
II
450k Ref detected
650k Ref detected
PLL Locked
200k Probe detected
PM Overflow
Trigger detected
Reset detected
FC Overflow
450k Probe detected
650k Probe detected
Figure 6: Data transfer format.
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Timing diagram of the digital phasemeter
t
d
t
1
Trig
REQ
START
STOP
STROBE
OE1
A0
A1
OE2
OE3
OE4
• Level high!: 3.3 V (TTL compatible)
• Timing
Unit Min Max Remarkt1 µs 0.2 5.2 Variabled µs 0.35 1 Programmablet µs 0.25 1 Programmable
Figure 7: Timing diagram of the data transfer.
Institute of Microtechnology, Neuchâtel OS, 28.8.2003
18
Input Description Location Connector
Ref
D IN 200kHz Input of the 200 kHz reference signal Front SM-A
FC IN Input of the 450 kHz reference signal ” SM-A
DC REF 450kHz DC level of the 450 kHz reference signal Back (P2) DIN 41612
DC REF 650kHz DC level of the 650 kHz reference signal ” DIN 41612
MESR 450kHz 650 kHz reference signal for frequency measurement ” DIN 41612
MESR 650kHz 650 kHz reference signal for frequency measurement ” DIN 41612
Probe
D IN 200kHz Input of the 200 kHz probe signal Front SM-A
FC IN Input of the 450 kHz probe signal ” SM-A
DC PROBE 450kHz DC level of the 450 kHz probe signal Back (P2) DIN 41612
DC PROBE 650kHz DC level of the 650 kHz probe signal ” DIN 41612
MESP 450kHz 650 kHz reference signal for probe measurement ” DIN 41612
MESP 650kHz 650 kHz reference signal for probe measurement ” DIN 41612
Trig Trigger signal from TIM Back (P2) LEMO
Reset Reset signal from TIM ” LEMO
All input signals must be 0−5V TTL compatible signals.
Output Description Location Connector
Inst Phase Instantaneous phase Front AMP 2-174225-5
Data bus 32-bit data bus, balanced Back (P2) Robinson
Strobe Strobe signal for data bus transfer ” Robinson
Table 6: Input and outputs of the digital phasemeter board. SM-A: SM-A female; LEMO: LEMO CA-MAC unipolar series 00; DIN 41612: DIN 41612 3×32 male; AMP 2-174225-5 2×34 male; Robinson:Robinson Nugent #P50E-080-S-TG.
Value Size Unit
Summed phase 48 bits 1LSB= 2π/1024rad
Error compensation 24 bits 1LSB= 0.66µm
Signal level of photodetectors 8 bits 1LSB= 7mV
Table 7: Units used for the values on the data bus.
Instantaneous phasemeter resolution 2π/1024
Internal sampling rate 200 kHz
Noise Equivalent Power of the photodetectors 0.14pW/√
Hz
Bandwidth of the input filters 110 kHz(±55kHz)
Saturation level of the photodetectors 1.4µW (optical) or 1.7 V
Nominal value of electrical inputs (INEL1/2, Probe/Ref) 0 dBm
Maximum value of electrical inputs (INEL1/2, Probe/Ref)27 dBm
Table 8: Summary of the phasemeter performance
OS, 28.8.2003 Institute of Microtechnology, Neuchâtel
19
9 Experimental tests
9.1 Electrical tests
Test of the phasemeter board
Two frequency generators with their time base locked to each other will be used to generate two squaresignals at 200 kHz. The phase between the signals will be varied and the instantaneous phase will bemonitored.
Test of the whole system
The same frequency generators will be used to generate sine signals at 450 and 650 kHz fed to theelectrical inputs of the preamplifiers and filters board. The phase between the signals will be varied andthe instantaneous phase output of the phasemeter will be monitored. The test will be repeated for differentinput levels. The corresponding optical power in each arm can then be calculated and the minimal opticalpower required for proper operation of the phasemeter can be deduced.
9.2 Dynamic tests
Target
Reference Mirror
l/4
Is(t)Ir(t)l1
AOM
AOM
PBS
PBS
BS PBS
PBS
P PL
OPDU
Translation stage or loudspeaker
Figure 8: Simulation of the motion of the delay lines.
Figure 8 shows the setup that will be used to simulate the movement of the delay lines. The commonpath will be modulated by means of a translation stage or a loudspeaker.
Figure 9 shows the setup that will be used to simulate the movement of the differential delay line. TheOPDU should be able to monitor the displacement of the mirror moving with a speed of 15 mm/s.
9.3 Tests of accuracy
Because of the stringent requirements, the test of accuracy over 120 mm with a one-wavelength sourceis a very difficult task. This would require a mechanical stability better than 5 nm. This stability is very
Institute of Microtechnology, Neuchâtel OS, 28.8.2003
20
Target
Reference Mirror
Is,1(t)Ir,1(t)l1
AOM
AOM
PBS
PBS
BS PBS
PBS
P PL
Translation stage or loudspeaker
Is,2(t)
Ir,2(t)
Figure 9: Simulation of the motion of the differential delay line.
Target
Reference Mirror
l/4
Is(t)Ir(t)l1
l2
AOM
AOM
PBS
PBS
BS PBS
PBS
P PL
Figure 10: Two-wavelength interferometry with superheterodyne detection.
difficult to obtain in laboratory. In addition, the refractive index of the air must be controlled to achievethe required 10−8 accuracy.
Two-wavelength interferometry allows to generate synthetic wavelengthsΛ = c/∆ν much longer thanthe individual optical wavelength. This allows to extend the range of non-ambiguity and to reduce thesensitivity of the measurement. The mechanical stability at the optical wavelength is thus not requiredany more. For instance, assuming a synthetic wavelength of 200 mm, a mechanical stability of 0.1 mmis required to demonstrate 2π/1000. This mechanical stability is obviously easy to achieve in laboratory.The setup depicted in Fig. 10 will be used for these tests.
The Nd:YAG lasers will be stabilized at a frequency difference of 1.5 GHz, corresponding to a syntheticwavelength of 200 mm by measuring the beat frequency resulting from the superposition of the two laserbeams.
9.4 Tests by comparison with a HP interferometer
In order to check the accuracy of the metrology prototype in a polarizing configuration, we can measurethe variations of a common optical path difference using both the metrology prototype and an industrial
OS, 28.8.2003 Institute of Microtechnology, Neuchâtel
21
HP laser
PBSC C
C C
HP det.
PBS
PBS
n-40 MHz
n-39.55 MHz
n+38.65 MHz
n+38 MHz
Probe 450 kHz
Ref 450 kHz
Probe 650 kHz
Ref 650 kHz
FC
Figure 11: Setup that will be used for tests by comparison with a HP interferometer. PBS, polarizingbeamsplitter; CC, corner cube; FC, fiber coupler; HP det, Hewlett-Packard detector.
interferometer (Hewlett-Packard 5517A). Figure 11 shows the setup that will be used.
9.5 Tests with long delay lines
The setup of Fig. 12, using a 1 km long fiber, can be used to simulate a long baseline interferometer. Thetwo heterodyne interferometers share a common optical path difference of 1.5 km. The observation ofthe phase of the individual 450 and 650 kHz signal as well as the phase difference makes it possible todetermine the fluctuations of the phase difference.
Institute of Microtechnology, Neuchâtel OS, 28.8.2003
22
n+38.65 MHz
n-39.55 MHz
n-40 MHz
n+38 MHz
Ref 450 kHz
Ref 650 kHz
FC
Probe 450 kHz
Probe650 kHz
FC
1 km fiber delay
PC
P
P
Figure 12: Setup that will be used to simulate long delay lines. P, polarizer; FC, fiber coupler; PC,polarization controller.
OS, 28.8.2003 Institute of Microtechnology, Neuchâtel
Institute of Microtechnology, Neuchâtel OS, 27.3.2003
A
Annex A
Global sketch of the phasemeter
Synoptique.Sch
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Modifié
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4-May-2003
/Sch.N°:Fichier: 1 1Page:
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:Heure : 20:34:44
10/01/03Phase mètre : Schéma synoptique
Rue A.-L. Breguet 22000 Neuchâtel
Photodetector
MixerU8
SRA-6
ZsZe
5050
U7
G=11.6 dB
F1
450 kHz
ZsZe
50HI
U9
G= 0 dB
Low pass filter
40 kHz
ZsZe
5050
U3
G=12 dB
Converter
TTL
TTL
U12
INOPT1
INEL1
DET1 OUT
OUT 450 kHz D OUT 450 kHz
DC REF 450K
1.2 V/u W
InGaAs
INOPT2
INEL2
DET2 OUT
Windowcomparator
TTL
Adj
U4
ZsZe
50HI
U2
G=0 dB
Converter
TTL
TTL
U12
OUT 650 kHz
DC REF 650K
MESR 450 kHz
G=-7dB
J14-B1
J14-A1
PROBE
REF
ZsZe
50HI
U8
G=28.8 dB
TV1
G=13 dB
J2-A2
FC OUT
A IN 450 kHz
D OUT 650 kHz
Windowcomparator
TTL
Adj
U5
ZsZe
50HI
U10
G=0 dB
Converter
TTL
TTL
U13
MESR 650 kHz
ZsZe
50HI
U16
G=28.8 dB
TV3
G=13 dB
J2-B2
A IN 650 kHz
MESP 450 kHz
J2-C3
MESP 650 kHz
J2-C4
TV1
G=12 dB
Band pass filter AmplifierZsZe
5050
U5
G= 11.6 dB
Amplifier
Photodetector ZsZe
5050
U13
G=11.6 dB
F2
650 kHz
ZsZe
50HI
U15
G= 0 dB
Low pass filter
40 kHz
1.2 V/u W
InGaAs
G=-7dB
TV2
G=12 dB
Band pass filter AmplifierZsZe
5050
U11
G= 11.6 dB
Amplifier
LIMITER
PROBE
DC PROBE 450K
DC PROBE 650KJ14-C2
J14-C1
AC Limiting Amplifier Amplifier
Buffer
TV1
G=0 dB
ZsZe
5050
U2
G= AdJ
Amplifier
AmplifierF1
200 kHz
G=-7dB
Band pass filter
ZsZe
5050
U4
G= Adj
AmplifierD OUT 200 kHz
D IN 450 kHz
TV2
G=0 dB
ZsZe
5050
U10
G= AdJ
AmplifierD IN 650 kHz
Photodetector ZsZe
5050
U8
G=11.6 dB
F3
450 kHz
ZsZe
50HI
U10
G= 0 dB
Low pass filter
40 kHz
INOPT1
INEL1
DET1 OUT
OUT 450 kHz
1.2 V/u W
InGaAs
INOPT2
INEL2
DET2 OUT
OUT 650 kHz
G=-7dB
TV3
G=12 dB
Band pass filter AmplifierZsZe
5050
U6
G= 11.6 dB
Amplifier
Photodetector ZsZe
5050
U14
G=11.6 dB
F4
650 kHz
ZsZe
50HI
U16
G= 0 dB
Low pass filter
40 kHz
1.2 V/u W
InGaAs
G=-7dB
TV4
G=12 dB
Band pass filter AmplifierZsZe
5050
U12
G= 11.6 dB
Amplifier
D OUT 450 kHz
FC OUT
A IN 450 kHz
D OUT 650 kHzA IN 650 kHz
MixerU9
SRA-6
ZsZe
5050
U6
G=12 dB
Converter
TTL
TTL
U13
TV3
G=0 dB
ZsZe
5050
U5
G= AdJ
Amplifier
AmplifierF2
200 kHz
G=-7dB
Band pass filter
ZsZe
5050
U7
G= Adj
AmplifierD OUT 200 kHz
D IN 450 kHz
TV4
G=0 dB
ZsZe
5050
U11
G= AdJ
AmplifierD IN 650 kHz
MIXER
REF REF REF
PROBE
PROBE
D IN 200 kHz
FC IN
TRIG
RESET
D IN 200 kHz
FC IN
DIGITAL PM
PREAMPFILTER
Buffer
Buffer
Buffer
Buffer
AC Limiting Amplifier Amplifier
Buffer
Windowcomparator
TTL
Adj
U6
ZsZe
50HI
U3
Converter
TTL
TTL
U14
ZsZe
50HI
U9
G=28.8 dB
TV5
G=13 dB
Windowcomparator
TTL
Adj
U7
ZsZe
50HI
U11
G=0 dB
ZsZe
50HI
U17
G=28.8 dB
TV7
G=13 dB
AC Limiting Amplifier Amplifier
Buffer
AC Limiting Amplifier Amplifier
Buffer
Converter
TTL
TTL
U15
G=0 dB
OverLoadProtection
OverLoadProtection
OverLoadProtection
OverLoadProtection
J66
Institute of Microtechnology, Neuchâtel OS, 27.3.2003
Institute of Microtechnology, Neuchâtel OS, 27.3.2003
G
Annex G
Front panel connections of
the phasemeter boards
SchCablage.Sch
TITREDessinéDate
Modifié
GROCCIA
5-May-2003
/Sch.N°:Fichier: 1 1Page:
::
:Heure : 13:07:32
4/05/03Phase mètre : Schéma de câblage
Rue A.-L. Breguet 22000 Neuchâtel
PhotodetectorINOPT1
INEL1
DET1 OUT
OUT 450 kHz D OUT 450 kHz
DC REF 450K
1.2 V/u W
InGaAs
INOPT2
INEL2
DET2 OUT
OUT 650 kHz
DC REF 650K
MESR 450 kHz
J14-B1
J14-A1
PROBE
REF
J2-A2
FC OUT
A IN 450 kHz
D OUT 650 kHz
MESR 650 kHz
J2-B2
A IN 650 kHz
MESP 450 kHz
J2-C3
MESP 650 kHz
J2-C4
Photodetector1.2 V/u W
InGaAs
LIMITER
PROBE
DC PROBE 450K
DC PROBE 650KJ14-C2
J14-C1
D OUT 200 kHz
D IN 450 kHz
D IN 650 kHz
PhotodetectorINOPT1
INEL1
DET1 OUT
OUT 450 kHz
1.2 V/u W
InGaAs
INOPT2
INEL2
DET2 OUT
OUT 650 kHzPhotodetector1.2 V/u W
InGaAs
D OUT 450 kHz
FC OUT
A IN 450 kHz
D OUT 650 kHzA IN 650 kHz
D OUT 200 kHz
D IN 450 kHz
D IN 650 kHz
MIXER
REF REF REF
PROBE
PROBE
D IN 200 kHz
FC IN
TRIG
RESET
D IN 200 kHz
FC IN
DIGITAL PM
PREAMPFILTER
J29 J6
J35 J7
J30J15 J32
J33
J53
J31 J16
J20 J21 J6 J10
J15
J12 J13 J5
J9 J18 J19
J34 J8
J38 J9
J36J17 J37
J40
J54
J39 J18
J41 J10
J47 J11
J42J19 J44
J45
J55
J43 J20
J46 J12
J50 J13
J48J21 J49
J52
J56
J51 J22
J22 J23 J7 J11
J16 J17 J8 J12
J14
J18 J19 J9 J13
J15 J17 J7
J10 J22 J23
J14 J16 J6
J20 J21 J8
J66
J60
J61
J64
J65
J62
J63
GND
GND
GND
GND
OverLoadProtection
OverLoadProtection
OverLoadProtection
OverLoadProtection
Institute of Microtechnology, Neuchâtel OS, 8.5.2003
H
Annex H
Datasheet of the Photodetector
InGaAs photodetector. Frequency and noise spectra.
-40
-30
-20
-10
0
10
20
Am
plitu
de [d
B]
101
102
103
104
105
106
107
108
Frequency [Hz]
-300
-200
-100
0
100
200
Phase [deg]
-140
-120
-100
-80
-60
Am
plitu
de [d
Bm
/Hz]
102
103
104
105
106
107
Frequency [Hz]
-140
-120
-100
-80
Am
plitu
de [d
Bm
/Hz]
2.0x106
1.51.00.50.0Frequency [Hz]
7.5MHz @-3dB
-128dBm/Hz
Fig. 2: 100Hz to20MHz
Fig. 3: 10Hz to2MHz
Fig. 1
-115dBm/Hz
InGaAs photodetector.Specifications: Photodiode 100um InGaAs pigtailedResponse 800 to 1800nm (Fig.4)Transimpedance gain 1.4 x 10 exp 6 V/ABandwith DC to 7.5MHzOut Voltage in Volt/uW, @1300 nm 1.2 V/uWOutput impedance 50 OhmsOutput voltage (50 Ohms ) 0 to 1.7 VOutput voltage (HI-Z ) 0 to 3.4 VOffset AjustableNoise (typical) from 10 Hz to 800KHz -128 dBm/HzNoise max @ 6MHz -115 dBm/HzNEP @1300nm 0.14 pW/rootHz
Power requirements +5V / 60mA Max +6V !0V common-5V / 60mA Max -6V !
Responsivity of the photodiode. Fig.4
Institute of Microtechnology, Neuchâtel OS, 23.5.2003
I
Annex I
PLD Design of the Phasemeter
MAX+plus II 9.6 File: PHASESHIFTER200-REF2QD-03-05-07.GDF Date: 05/08/2003 15:37:23 Page: 1
w2s
ReferenceINPUT
D
DFF
CLRN
QPRN
D
DFF
CLRN
QPRN
D
DFF
CLRN
QPRN
D
DFF
CLRN
QPRN
D
DFF
CLRN
QPRN
D
DFF
CLRN
QPRN
D
DFF
CLRN
QPRN
D
DFF
CLRN
QPRN
Clear INPUTC
Clock INPUTC
LPM_AVALUE=
LPM_DIRECTION=
LPM_MODULUS=
LPM_SVALUE=
LPM_WIDTH=10
updown
cnt_en
clk_en
q[]
LPM_COUNTER
LPM_AVALUE=
LPM_DIRECTION=
LPM_MODULUS=
LPM_SVALUE=
LPM_WIDTH= 9
cnt_en
clk_en
aclr
q[]
LPM_COUNTER
NOT
NOT
Clock2OUTPUT
PLLOUTPUT
Ref2OUTPUT
Clock1OUTPUT
RefQOUTPUT
VCC
VCC
VCC
VCC
TRI
RefQ
Reference
PS[8..0]
PLL,P[8..2],Clock2,P0
PS8 RefQ
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LPM_AVALUE=
LPM_DIRECTION=
LPM_MODULUS=
LPM_SVALUE=
LPM_WIDTH=10
sload
updown
cnt_en
data[]
clk_en
aclr
q[]
LPM_COUNTER
LPM_AVALUE=
LPM_DIRECTION=
LPM_MODULUS=
LPM_SVALUE=
LPM_WIDTH=19
updown1
cnt_en
clk_en
aclr
q[]
LPM_COUNTER
LPM_AVALUE=LPM_DIRECTION=
LPM_MODULUS=
LPM_SVALUE=
LPM_WIDTH=10
sload
updown
cnt_en
data[]
clk_en
aclr
q[]
LPM_COUNTER
RefQ INPUT
ReferenceINPUT
NoError INPUT
Clock INPUTC
Signal INPUTC
Clear INPUTC
D
DFF
CLRN
QPRN
D
DFF
CLRN
QPRN
D
DFF
CLRN
QPRN
D
DFF
CLRN
QPRN
D
DFF
CLRN
QPRN
D
DFF
CLRN
QPRN
D
DFF
CLRN
QPRN
D
DFF
CLRN
QPRN
D
DFF
CLRN
QPRN
D
DFF
CLRN
QPRN
D
DFF
CLRN
QPRN
D
DFF
CLRN
QPRN
D
DFF
CLRN
QPRN
D
DFF
CLRN
QPRN
D
DFF
CLRN
QPRN
D
DFF
CLRN
QPRN
D
DFF
CLRN
QPRN
D
DFF
CLRN
QPRN
D
DFF
CLRN
QPRN
D
DFF
CLRN
QPRN
D
DFF
CLRN
QPRN D
DFF
CLRN
QPRN
D
DFF
CLRN
QPRN
D
DFF
CLRN
QPRN
VCC
VCC
VCC
AND2
AND2
AND2
NOT
NOT
NOTNOT
NOT
NOT
F[9..0]OUTPUT
I[18..0]OUTPUT
ReadyOUTPUTC
LPM_AVALUE=
LPM_WIDTH=10
aclr
data[]
gate
q[]
LPM_LATCH
LPM_AVALUE=
LPM_WIDTH=2
aclr
data[]
gate
q[]
LPM_LATCH
LPM_AVALUE=
LPM_WIDTH=10
aclr
data[]
gate
q[]
LPM_LATCH
NOR2
XNOR
XNOR
XOR
WIDTH=10
result[]
datab[]
sel
dataa[]0
1
BUSMUX
LATCH
QENA
D
AND3
NOR3
OR2
Signal
A[9..0]
K1
Clock
CntB8
B9
Clear
A9
K[1..0]Cnt,UD
UDA8
Start2
K0
A7B[9..0]
SELECT
X1,X0,B[7..0]
X1
FR[9..0]FR[9..0]
A[9..0]X0
Clear
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