High Speed CMOS Photoreceivers and Technology for … · 2011. 3. 19. · Kamel AYADI . V E R S N I...

SREVINU

ITEIT

EJIR

V

BRUSS

EL

ECNIVRE TEN

EB

RA

S

AI

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EIC

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Vrije Universiteit Brussel Faculteit Toegepaste Wetenschappen

Applied Sciences Pleinlaan 2, 1050 Brussel, Belgium.

High Speed CMOS Photoreceivers and Technology for OptoElectronic ICs and

Data Communications

Kamel AYADI

SREVINU

ITEIT

EJIR

V

BRUSS

EL

ECNIVRE TEN

EB

RA

S

AI

TN

EIC

S

Vrije Universiteit Brussel Faculteit Toegepaste Wetenschappen

Applied Sciences Pleinlaan 2, 1050 Brussel, Belgium.

High Speed CMOS Photoreceivers and Technology for OptoElectronic ICs and

Data Communications

by Kamel AYADI

Doctorate in Applied Physics

1998

Kamel AYADI, Member, IEEE under number: 40214376

author’ correspondence: e-mail: [email protected] Office address: VUB, Applied Sciences Faculty, Pleinlaan 2, B-1050 Brussels, Belgium. Tel: ++32-2-6292985 - fax: ++32-2-6292870 http://etro.vub.ac.be/kayadi.html

SREVINU

ITEIT

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BRUSS

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ECNIVRE TEN

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i m e c

VUB, Vrije Universiteit Brussel, Faculteit Toegepaste Wetenschappen, Applied Sciences, Pleinlaan 2, B-1050 Brussel, Belgium. http://www.vub.ac.be

IMEC V.Z.W., the Interuniversity Microelectronics Center, Kapeldreef 75, B-3001, Leuven, Belgium. http://www.imec.be

Acknowledgements

I would like to thank all the people who have worked at the faculty of Applied Sciences during those three and a half years at the VUB university, Brussels, and IMEC the inter-university microelectronics center, Leuven, Belgium.

Special thanks to my promoter Prof. Erik Dirkx for supervising me, and his team Wouter Brissinck, Abdellah Touhafi, Sven Clarysse and Zhang Haiting from the Parallel System laboratory for the joyful moments that we have had at the department.

Also, I would like to thank Dr. Frank Tooley from the department of Physics, Heriot-Watt university, Scotland, UK, and Prof. Jacek Chrostowski from Photonic Systems group, National Research Council, Canada, for reading my Ph.D. thesis and their comments.

Thanks to Dr. Ted K. Woodward from Bell Laboratories, Lucent Technologies, Holmdel, NJ, USA, for his help for the photonic analysis and for his letter and his articles. Thanks to Prof. Palle Jeppesen and Prof. Per Danielsen from the department of Electromagnetic Systems, DTU university, Lyngby, Denmark, and Ir. Jan Pathuis, Laser Systems Nijmegen, Philips, Nijmegen, The Netherlands for their invitations and their offers for Jobs.

Also, thanks to the two authors of the articles that I added to my thesis text: Dr. Travis N. Blalock, USA, and Dr. Guoneng Lu, Paris 6, university, France, and their E-mails. I appreciate the technical information about the packaging of the Pentium processor that the Intel-staff gave me.

Finally, I would like to thank the members of the jury of this Ph.D. Thesis: Prof. Jacques Tiberghien (Applied Sciences faculty, VUB), Prof. Alber Carden (Applied Sciences faculty, VUB), Prof. Erik Stijns (Sciences faculty, VUB), Prof. Erik Dirkx (Applied Sciences faculty, VUB), Dr. Werner Peiffer (Philips, Hasselt), Prof. Willy Sansen (Applied Sciences faculty, KUL), and Dr. Jan Sevenhans (Alcatel Bell, Antwerpen), for the attention that they pay to this work, and I hope that it will be to their liking.

List of Publications and Conferences

1/ K. Ayadi, E. F. Dirkx, and J. M. J. Sevenhans, “High-Speed, High-Sensitive

OEIC Using Clocked Vertical BJTs PhotoDarlington in CMOS Technology,” accepted paper: May 1998 (under ref. M6065),

IEEE J. Solid-State Circuits. 1998. 2/ K. Ayadi, and E. F. Dirkx, “A Novel CMOS Photoreceiver Operating at High

Frequencies,” accepted conference, IEEE Photonics'98, New-Delhi, December 14-18, 1998. 3/ K. Ayadi, and E. F. Dirkx, “Influence of Light on the Operating Frequencies of

CMOS Transistors,” paper should be submitted, Appl. Physic. Lett., 1998.

4/ K. Ayadi, P. Heremans, M. Kuijk, C. D. Tandt, G. Borghs, and R. Vounckx,

“Combining a GaAs Thyristor - Based Optical Receiver with a 1-GHz CMOS Comparator Amplifier to Overcome Signal Delays,”

IEEE Circuits & Devices , vol. 13, no 4, pp. 24-29, July 1997. 5/ K. Ayadi, G. Bickel, M. Kuijk, P. Heremans, G. Borghs, and Roger Vounckx,

“A Hybridized Optical Thyristor-CMOS Receiver for Optoelectronic Application,”

IEEE Photon. Technol. Lett., vol. 9, no. 5, pp. 669-671, May 1997. 6/ K. Ayadi, M. Kuijk, P. Heremans, G. Bickel, G. Borghs, and Roger Vounckx,

“A Monolithic Optoelectronic Receiver in Standard 0.7-µm CMOS Operating at 180 MHz and 176-fJ Light Input Energy,”

IEEE Photon. Technol. Lett., vol. 9, no. 1, pp. 88-90, Jan. 1997. 7/ K. Ayadi, P. Heremans, M. Kuijk, C. D. Tandt, G. Borghs, and R. Vounckx, “A

180 MHz Standard CMOS Silicon Optoelectronic Receiver,” IEEE Circuits & Devices , vol. 13, no 1, pp. 26-28, Jan. 1997. 8/ P. Heremans, K. Ayadi, M. Kuijk, G. Bickel, R. Vounckx and G. Borghs, "Optoelectronic Integrated Receiver for Inter-MCM and Inter-Chip

Optical Interconnects," IEEE IEDM 96. San Francisco, CA. December 8-11 1996. pp 657-

660 (26.4.1-26.4.4), 1996.

9/ P. Heremans, M. Kuijk, G. Bickel, K. Ayadi, R. Vounckx, and G. Borghs, "Optoelectronic devices and switches for short-distance optical

interconnects," XXVth General Assembly of the International Union of Radio

Science (Union Radio-Scientifique) URSI; August 1996; Lille, France.

10/ M. Kuijk, K. Ayadi, P. Heremans, G. Bickel, G. Borghs, and R. Vounckx,

"Optical Chip Interconnections: Economically Viable ?," IEEE ICAPT 96. Montreal, CANADA, August 1996.

Ph.D. Jury List

Chairman: Prof. Dr. Ir. Jacques Tiberghien - Vrije Universiteit Brussel

Vice-Chairman: Prof. Dr. Ir. Alber Carden - Vrije Universiteit Brussel

Secretary: Prof. Dr. Ir. Erik Stijns - Vrije Universiteit Brussel

Promoter: Prof. Dr. Ir. Erik Dirkx - Vrije Universiteit Brussel

Invited: Dr. Ir. Werner Peiffer - Philips, Hasselt

Prof. Dr. Ir. Willy Sansen - KUL, Universiteit van Leuven

Dr. Ir. Jan Sevenhans - Alcatel Bell, Antwerpen

Table of contents

Chapter I Introduction 1

I.1 Abstract 1

I.2 The beginning of optoelectronic ICs 2

I.3 Hybridized and monolithic photoreceivers 2

I.4 Criticism 3

I.5 Outline of the text 3

Chapter II Hybridized Photoreceiver 5

II.1 Introduction 5

II.2 The GaAs detector 6 II.2.a Operation and measurement 6 II.2.b Interpretation 8

II.3 The CMOS comparator amplifier 9 II.3.a Topology and design 9 II.3.b Operation 9 II.3.c Simulation 10

II.4 Hysteresis of the comparator 11 II.4.a Theory and design consideration 11 II.4.b Measurements 13

II.5 Experimental results 14

II.6 Conclusion 17

Chapter III Physics of Photodetectors in a n-well CMOS Technology 19

III.1 Introduction 19

III.2 Photodetectors in CMOS technology 20 III.2.a Classic p-n photodiode 20 III.2.b N+/Psub photodetector 21 III.2.c P+/n-well/Psub photodetector 23 III.2.d Monolithic color detection 27 III.2.e Vertical pnp BJT photodetector 30

III.3 Deeply illuminating MOS effect (DIME) 31 III.3.a Introduction 31 III.3.b Transversal diffusion effect 31 III.3.c Photocarrier diffusion time analysis 33 III.3.d Interpretation 34

III.4 Measurement 36 III.4.a Setup considerations 36 III.4.b Dynamic operation 37 III.4.c Physics and photonic analysis 39 III.4.d Horizontal diffusion effect 42

III.5 Conclusion 45

Chapter IV Double-Beam Monolithic CMOS Photoreceiver 47

IV.1 Introduction 47

IV.2 Design and operation 48 IV.2.a Circuit design and simulation 48 IV.2.b Small-signal analysis 52

IV.3 Measurements and photonic interpretations 55 IV.3.a NMOS version 56 IV.3.b PMOS version 57 IV.3.c Photonic analysis 59

IV.4 Conclusion 59

Chapter V Single-Beam Monolithic CMOS Photoreceiver 61

V.1 Introduction 61

V.2 Detailed photoreceiver design and analysis 61 V.2.a Photoreceiver architecture 61 V.2.b Preamplifier circuit 63 V.2.c Post-amplifier circuit 65

V.3 Small-signal analysis 67 V.3.a Ideal analysis 67 V.3.b Entire analysis 70

V.4 Operational principle 72

V.4.a Photoreceiver circuit 72 V.4.b Photonic analysis 73

V.5 Simulations and discussion 74 V.5.a Hspice simulation 74 V.5.b From t = 20 ns to 40 ns 75 V.5.c From t = 40 ns to 60 ns 75 V.5.d From t = 60 ns to 80 ns 75 V.5.e From t = 80 ns to 100 ns 77 V.5.f Interpretation 77

V.6 Noise switching circuit affects 78

V.7 Experimental results 80

V.8 Conclusion 83

Chapter VI Technology and Optical Fiber for Inter-chip 85 Data Communications

VI.1 Introduction 85

VI.2 High-density Si based optoelectronic chip 87 VI.2.a Strategy 87 VI.2.b Design 87 VI.2.c Assemblage 89 VI.2.d Module description 91 VI.2.e Alignment 92

VI.3 Special considerations and performances 94 VI.3.a Design considerations 94 VI.3.b Waveguide processes 96 VI.3.c Multi-fiber connector 97 VI.3.d Loss in light propagation 97

VI.4 Conclusion 98

Chapter VII Conclusions 101

Appendices 103

A.1 Appendices 1 103

A.2 Appendices 2 106 A.2.1 Principal operation of CBLSA 106 A.2.2 Small-signal analysis 107

References 111

Index 119


Chapter I

Introduction

I.1 Abstract

In Microelectronics, information between chips is usually transferred by the use of metal lines (wires). The performance of electronic integrated circuits will keep improving in the coming 10 years. However, the information exchange between chips (inter-chip) and on chip (intra-chip) is becoming a serious bottleneck at high frequencies above 500 MHz.

Inter-chip; an electrical line induces a strong delay in the information transfer, and the number of lines (pincount) cannot be increased indefinitely (the maximum is a few hundred). Intra-chip, when VLSI (Very Large Scale Integration) structures with many millions of transistors are fabricated in a single chip, the high number of interconnections between all these transistors starts posing problems. The area of VLSI chips is at least 1 cm2 and ULSI (Ultra Large Scale Integration) chips are expected to be one order of magnitude larger for the next generation [Giannelis93]. The communication between the different circuit blocks needs long interconnection paths of about 1 to 10 cm [Dagenais95].

The signal delays due to the charging of the high capacitance of these interconnections between the metal lines become a significant part of delays in integrated systems, and thus attenuate the frequency of the system [Iwata94,

2 Chapter I Introduction

Bohr95]. Also, the need of thousands of I/O pads in a VLSI chip occupy a considerable area on chip.

An alternative to this classical line interconnection is the use of photons instead of electrons. In this case one talks about optical interconnects and optoelectronic IC (OEIC). Photons can carry signals at the highest possible speed without using any wires because they have no charge, as opposed to the situation for electrons, which suffer from the RC time of metal wires for long distance interconnections and at high frequencies.

I.2 The beginning of optoelectronic ICs

Early OEIC experiments [Yariv84] have been demonstrated in 1978-79 in [Lee78, Yust79]. Since the evolution of OEIC towards large scale integration, GaAs- InP-emitter/receivers are considered suitable for OEIC applications [Dagenais90] due to their small areas, low noise and very high frequency.

Yet, success depends on high yields in main stream Si-based material. Si IC processes are well developed and have a high yield, and single-chip modules are lower in cost and higher in reliability than multi-chip modules [Nagao89]. This makes Si IC technology more attractive to evaluate for Si OEIC photoreceivers, because the realization of a high speed photoreceiver in CMOS technology offers the possibility to incorporate the sensor and the processing circuitry in a single IC [Ayadi97a].

However, the main speed limitation of Si OEIC is due to the absorption depth necessary for efficient generation of photocarriers, which is over 10 µm for 800- to 900-nm laser injection [Sze81]. This total depth must be depleted by a very high bias voltage if the device speed is not to be limited by photocarrier diffusion current.

I.3 Hybridized and monolithic photoreceivers

One solution to the speed limitation of silicon photoreceivers is the development of a hybrid photoreceiver in which the photoabsorption layer is grown in another material with high electron mobilities such as GaAs or InP and is connected to the silicon substrate [Ayadi97c, Dagenais90]. The use of the flip-chip technique is necessary to achieve packages with low parasitic capacitance [Sussmann85]. This technique is difficult and very expensive compared with a monolithic Si photoreceiver which main feature is its potential for cost savings and size reduction.


The use of the inexpensive standard Si CMOS technology for implementing photosensors has been reserved during the last years for charge-coupled devices and silicon retina applications, see [Espejo94, D.-Castro97, Wu95a]. The reason is that the response speed of the CMOS photosensor is deeply limited by the diffusion of the generated carriers in the bulk, which makes these structures extremely slow in the kHz range. Hence it is acceptable for image detection applications but unsuitable for VLSI optical interconnections.

The improvement of photoreceivers towards high speed Si OEIC photoreceivers are rendered possible through our work, as has been demonstrated recently in [Ayadi97a] by the injection of competing double-optical pulses at a frequency of 180 MHz, and in [Ayadi98a] by injecting single-optical pulses at a frequency of 100 MHz. This proves that the operating speed is limited by circuit-design considerations and techniques rather than by the local photodiode performances.

I.4 Criticism

In SPIE "The critical reviews of optical science and technology", a recent article was reported by David A. B. Miller in [Miller98] and discussed our work by saying: "... The resulting carriers can take a long time to diffuse back into the junction region where they eventually give rise to additional photocurrent. This can lead to very long tails on the response of Silicon photoreceivers, for an example of recent high-speed CMOS photodetector work, see Ayadi ..." and finished by: "... With compound semiconductor photodetectors, there appears to be little problem with achieving speeds in the gigahertz range with good efficiencies.".

It is true that the CMOS photoreceivers that we develop have demonstrated high operating frequencies in their first try, but with low efficiencies. We improved, recently, with one order of magnitude the efficiency of the photoreceivers. We will continue to bring more improvement in dynamic range by injecting other wavelengths of laser and by using new techniques such as the horizontal injection of light.

I.5 Outline of the text

In this thesis, we present solution circuits to overcome the frequency limitations of CMOS photoreceivers. Hybridized and monolithic photoreceivers are developed and are detailed here. Techniques for the realization of

4 Chapter I Introduction

optoelectronic systems and technology for optical I/O inter-chips are also presented.

Chapter II introduces our hybridized GaAs-Si photoreceiver and its performance. The physics of p-n photodiodes available in an n-well CMOS technology is detailed in chapter III. Monolithic CMOS double-beam and single-beam photoreceivers are revealed in chapter IV and chapter V, respectively. In chapter VI, we discuss the techniques for the realization of high-density Si-based optoelectronic chips and their packages for communications at high frequencies. Optical fibers, waveguides and other passive optical devices are used for interconnection of chips of the next generation, which will be the optoelectronic.

Chapter II Hybridized photoreceiver 5

Chapter II

Hybridized Photoreceiver

II.1 Introduction

We describe here our participation in the integration of two different based materials for achieving one function. This kind of integration is called hybrid. The reason using different materials together, in spite the technology difficulty and the cost for build, is to perform efficiently the function or because of the limitation of the dominate material to achieve one part of work (e.g., emission of laser by silicon material ? in [Hirschman96]).

In contrast to electrical interconnects, the cost and complexity of optical interconnects barely increase with increasing interconnect length. This is of great value for future scaled-down technologies. However, the introduction of optical interconnect technologies in VLSI faces several challenging problems, amongst which the choice of a proper long-lived light-emitter and of a small and sensitive receiver, not to mention the requirement of a robust optical pathway and of a yielding interconnect technology between CMOS circuitry and III-V emitters and/or receivers.

The boundary conditions for the light emitters and receivers are the area required on the silicon chip for their drivers, the power consumption, and the required clock speed. The maximum required clock speed is that of the processor clock, i.e., 500 MHz to 1 GHz. Compared to long distance optical

6 Chapter II Hybridized photoreceiver

interconnects, this is reasonably slow, and hence it leaves room to use simple and robust technologies both for light emission and light detection. Some examples of small, low power detector/converters are described in [Ayadi97a, Woodward96a].

In this chapter, we present a highly-promising receiver for the above-described application. It concerns the integration of an ultrasensitive III-V detector [Hara89, Taylor86] with a dedicated CMOS comparator amplifier [Ayadi97c, Ayadi97d]. The III-V detector is a differential pair of optical thyristors, which has been shown to operate at 155 MBits/s and require optical inputs of only 3 fJ [Bickel97] and no dc consumption. It delivers an analog output which is amplified to logic levels in the CMOS comparator amplifier.

Our participation in build of an emitter-receiver is to design an adequate CMOS comparator and to connect it by bond-wiring to the thyristor pair.

II.2 The GaAs detector

In this section, we discuss in detail the control of the thyristor pair under reception of a differential optical input signal and the necessity of a comparator amplifier for conversion of a differential analog signal from the pair to a logic signal. Fig. II.1 shows the III-V optical thyristor differential pair connected to our dedicated CMOS comparator amplifier. The thyristor pair, including the resistances RA, RB and RC, is made in the GaAs/AlGaAs material system

[Heremans92].

TAinput light

TB

+outSiA

outSiB

clock driver

RA RBPA PB

RC inSiA

inSiB

Figure II.1 Configuration of the hybridized photoreceiver. Thyristor pair is bonded by wires to the comparator amplifier.

II.2.a Operation and measurement

The differential pair works according to dual-rail code logic: with thyristor TA of the pair in its conductive on-state and thyristor TB in its high-impedant off-


state, the pair is considered to be in the Boolean "0" state; conversely, with TB ON and TA OFF, the pair is in the "1" state. An input light pulse on TA, respectively TB, triggers the pair into its "0", respectively "1", state. The (analog) electrical output of the pair is a voltage difference between the output pads PA and PB (Fig. II.1). This voltage difference is sensed and amplified to logic levels

by the CMOS comparator amplifier [Ayadi97c].

li ght at TA li ght at TB

4.5

0

-4.5

3.5

0

-4

Ø1 Ø3Ø2

Ø3aØ3b

time (s )

time (s )

cloc

k dr

iver

(V)

P A (V

)P B

on-voltages

Figure II.2 Diagram representation of the clock driver and output signals from thyristor pair.

More details about the operation are revealed in Fig. II.2. The thyristor pair is driven by a three-phased clock driver.

First comes a reset-phase (φ1): a pulse at -4.5 V is given to sweep out all the

carriers from the inner thyristor layers, such as to erase the memory of the pair for its previous state [Kuijk94]. During the subsequent phase φ2, the voltage

over the pair is brought to zero, and an optical input, synchronized to the clock driver, is given to either TA or TB, representing respectively an incoming "0" and "1". In the third phase (φ3), 4.5 V pulse is given to the pair. The thyristor of the

pair that has previously received the optical input switches ON, and conducts current, whereas the other thyristor of the pair remains OFF.

The switch-on process can be monitored by measuring the voltage at PA and PB as shown in Fig. II.3. During the transition of the driving voltage from 0 to 4.5

V, the voltage over both thyristors increases to about 3.5 V. During the subsequent steady period at 4.5 V, the two thyristors compete for switching ON. Initially the voltage over both remains 3.5 V. The length of this period, which lasts for about 4 ns and is denominated φ3a in Fig. II.3, is determined by the


driving current through the thyristor pair, i.e., by the voltage and the resistances. Then, the voltage drops because one thyristor starts switching ON.

A leveling OFF occurs to a voltage of about 1.37 V for the winner and 1.73 V for the loser. This phase is referred to as phase φ3b in Fig. II.2. It lasts for as

long as the driving voltage is kept high, i.e., during about 6 ns in Fig. II.3. It is the voltage difference of 0.36 V occurring during this phase φ3b that the CMOS

comparator amplifier is to detect. Finally, when the driving voltage plunges to -4.5 V again (φ1), the voltage over both thyristors drops to approximately -4 V.

4

2

0

-2

-4

volta

ges

(V)

403020100

time (ns)

clock driver

PA

PB

Ø3a Ø3b Ø1 Ø2

Figure II.3 Measured output signals of the thyristor pair when TA receives light.

The thyristor pair is fabricated in the GaAs-AlGaAs material system [Heremans96], and is grown by Molecular Beam Epitaxy [Taylor86]. Each thyristor is 30 x 45 µm2, and the pair is 100 x 120 µm2. The pair was shown to operate with optical inputs as small as 3 fJ [Bickel97]. Its present speed limit is about 155 MHz [Bickel97].

II.2.b Interpretation

The output voltages PA and PB are therefore large common-mode (during phases φ1 and φ3a), and small common-mode (during φ3b). It is difficult to

convert them to comprehensible logic signals by using a standard CMOS comparator amplifier, because the comparator will not be stable from one phase to the next. A new comparator topology with fully differential topology was developed for this conversion. The comparator should have a high input impedance for not disturbing the switching of the thyristor pair, and a wide common-mode range to accommodate different thyristor layer structures (with


associated different on-voltages, see Fig. II.2). High speed operation will minimize the delay associated with this comparator stage.

II.3 The CMOS comparator amplifier

II.3.a Topology and design

Fig. II.4 shows the designed three-stage CMOS comparator amplifier. This novel comparator amplifier was designed [Ayadi97c] and fabricated in a 0.7-µm 5-V n-well CMOS technology, single poly double metals. The input stage is formed by the complementary pairs (M1, M3) and (M2, M4) which accept the differential input, and a current mirror (M5, M6). The amplification stage contains an internal positive feedback loop (M7, M8) stabilized by (M9, M10). The output stage is formed by a dynamic R-S flip-flop M11 to M18 [Kacprzak87], which assures non-return-to-zero (NRZ) of the output signal.

Vdd

G ROU N D

M5 M6

M7

M4M3

M1 M2

M10 M16

M18M9M15

M17

M13

M11 M12

M14I8

I7ou tSiA ou tSiB

inSiA in SiB

M8

Figure II.4 Topology of the comparator amplifier.

II.3.b Operation

The operation of our novel comparator [Ayadi97c] is as follows:

We start with phase φ3a, during which both inputs are at about 3.5 V (see

Fig. II.2 and II.3). The outputs of inverters (M1, M3) and (M2, M4) are then low, whereas the floating sources of M3 and M4 are at a high voltage. Therefore, transistors M7 and M8 are both in the triode regime. As we then move into


phase φ3b, the inputs decrease to, say inSiA = 1.37 V and inSiB = 1.73 V. The

output of the inverter (M1, M3) is higher than that of (M2, M4), hence M8 conducts more current (I8) than M7 (I7). This positive feedback brings the output of (M1, M3) to 5 V and that of (M2, M4) to zero. During this process, M8 remains in the triode regime, while M7 enters saturation and finally cuts OFF.

During the next phase (φ1) both inputs go to approximately -4 V, turning OFF

M1 and M2. This situation is kept during φ2, with both inputs at zero volt.

Transistors M8, M5 and M3 are ON, assuring that the output of inverter (M1, M3), also being the drain of M9 and the gate of M10, remain at 5 V. The gate of transistor M10 being at 5 V, its drain is connected to the ground, effectively keeping the output of inverter (M2, M4) at 0 V. The gate of M9 is hence at zero volt. In this way, transistors M9 and M10 assure that the output acquired during φ3b is kept during φ1 and φ2.

During the subsequent phase φ3a, M3 and M4 are turned OFF. The drains of

both M9 and M10 are brought to zero by M1 and M2 which are ON. We now rely on the operation of the R-S flip-flop, extensively studied in [Kacprzak87], to save the output voltages acquired during φ3b at the outputs outSiA and outSiB.

II.3.c Simulation

Fig. II.5 shows simulation of the operation obtained by Hspice. The maximum frequency shown is 1 GHz, and on-voltages of only 100 mV. At this speed the dissipated power is 200 mW for a 1 pF load output capacitance and only 400 µW with load capacitance of 50 fF. Table II.1 summarizes the device dimensions of Fig. II.4 used for simulations at frequency of 1 GHz and for measurements at high frequency, about 250 MHz. Hspice input file appears in appendix 1.

Table II.1 Comparator amplifier MOSFET dimensions (W/L).

simulations at 1 GHz

measurements at 50 MHz

M1, M2 200/0.7 4/0.7

M3, M4 350/0.7 4/0.7

M5, M6 10/0.7 1/0.7

M7, M8 250/0.7 3/0.7

M9, M10 100/0.7 1/0.7

M11-M14 350/0.7 8/0.7

M15-M18 150/0.7 4/0.7


Figure II.5 Simulation result of the comparator amplifier at frequency of 1 GHz.

II.4 Hysteresis of the comparator

Our comparator is very fast, and hysteresis is required to accommodate noisy inputs from the thyristor pair. This hysteresis must be controlled during design stage in order to assure a good stability to the comparator without affecting its sensitivity to the input voltages. The presence of an internal positive feedback loop (M7, M8) leads to internal hysteresis. Thus the steady of this phenomenon is one of the principle procedure to develop CMOS comparator.

II.4.a Theory and design consideration

It is interesting to minimize the hysteresis of the comparator amplifier, and the objective of this work is to deduce the transistor geometry widths W7 and W8 of the current feedback [Filanovsky95].

Let the input voltages VinSiA be 1.4 V and VinSiB be 1.25 V then M5, M6, and M8 are ON and M7 is off. If VinSiA decreases and VinSiB increases, the

comparator changes state. When M8 is forced into pinch off operation but has


not yet conducted any current, the positive current-feedback loop M7 is in pinch off operation. At this point I8 = n I6 , I7 = 0 and I4 = I6 .

Assuming that I6 = I5 , we can write

I3 = n I6 + I5 = n + 1( )I5 (II.1)

I3 + I4 = Itotal (II.2)

then

Δ I = I3 − I4 =n

n + 2⎛ ⎝ ⎜ ⎞

⎠ ⎟ Itotal (II.3)

1.25

1.00

0.75

0.50

0.25

0.00

10.07.55.02.50.0

Δ Vhys

Itotalβ n

n

Figure II.6 Hysteresis width versus width ratio.

The introduction of the common mode in this relation gives

Δ I = ΔV βn2Itotal

βn− ΔV( )2 (II.4)

where

ΔV = Vgs3 −V gs 4 (II.5)

βn =μn εo εox

tox

WL

⎛ ⎝ ⎜ ⎞

⎠ ⎟ (II.6)


with W and L are the channel width and length, respectively, of the concerned transistor. tox is the gate oxide thickness, εox is the permittivity of dielectric oxide, μn is the electron mobility, and εo is the permittivity of free space.

From (II.3) and (II.4) the hysteresis loop width is

ΔVhys = 2 ΔV = 2Itotal

βn1−

2 n + 1n + 2

⎛

⎝ ⎜

⎞

⎠ ⎟

(II.7)

The normalized plot of this equation (II.7) is shown in Fig. II.6, and the curve demonstrates that if n increases the hysteresis width increases too.

During the last steady, the influence of the complementary input (M1, M3) and (M2, M4) are not taken into account in case to extract separately the participation of the concerned parts in hysteresis. Itotal is the total flow current through (M1, M3) and (M2, M4). This current plays a significant role in hysteresis when an anomaly in the dimensions of these inverters happens.

II.4.b Measurements

2.4

2.2

2.0

1.8

1.6

1.4

1.2

1.0

hyst

eres

is o

f the

com

para

tor

(V

)

87654321

channel widths of M1 and M2 (µm)

VTRP-

VTRP+

Figure II.7 Measurement of comparator hysteresis. The area enclosed by the two curves VTRP+ and VTRP- defines the hysteresis range. For small channel widths of M1 and M2, the hysteresis area becomes wider due to a more positive feedback in the comparator.

Under phase φ3b, the outputs do not change until the inputs reach (on both sides) the positive trip point, VTRP+, and the negative trip point, VTRP-. The


noise of the inputs created within these two voltage levels can not disturb the switching of the outputs. Fig. II.7 shows the experimental result of the hysteresis of the comparator as function of the channel widths WM1 and WM2 of

transistors M1 and M2 (causing negative feedback).

The maximum large-signal output-voltage, Vout, e.g., of one complementary input, increases for a decreasing in WM1 from 8 µm to 1 µm, and it reaches the source voltage, VS3, of M3 for the given size of WM1, see Fig. II.8. VTRP- and VTRP+ vary widely with WM1 while VS3 is dependent on the ratio of the transconductance parameters β8 β6 of M8 and M6. The choice of WM1 and WM2 is therefore dependent on the hysteresis needed in the comparator

amplifier.

Vout

Vin

W M1=1µm

8 µm

VTRP+VTRP-

VS3 . . .

Vin Vout

VS3

M3

M1

Figure II.8 dc transfer curve of one complementary input, showing the location of VTRP- and VTRP+.

External effects as temperature, package in use, and mismatch between transistors keep continually the hysteresis in the comparator as shown in Fig. II.7. We believe that an external positive feedback is done and it raises the total positive feedback of the circuit.

II.5 Experimental results

The area of the comparator amplifier is 40 x 45 µm2 (without pads and external buffers). The electrical interconnection between the silicon die and the GaAs die was done by wirebonding (package of 40 pins, large cavity), see Fig. II.9.

Fig. II.10 shows the experimental verification of the operation of the III-V differential thyristor pair in combination with the dedicated CMOS comparator amplifier. Two laser diodes with a wavelength of 830-nm provide the optical


Figure II.9 Photograph of the silicon and the GaAs dies that were connected by wirebonding. To measure the digital outputs, outside the silicon chip, output buffers were foreseen. Their capacitive output load during tests was about 5 pF.

6

4

2

0

-2

-4

clo

ck d

rive

r (V

)

opt

ical

inpu

t pul

ses a

t TA

, TB

(a.

u.)

5

4

3

2

1

0

time (ns)

silic

on o

utpu

ts (

V)

outSiB

outSiA

opt

ical

inpu

t pul

ses a

t TA

, TB

(a.

u.)

0 200160 18014012010080604020

A AAAB BBBBB

B A BBBB B AAA

Figure II.10 Given electrical and optical inputs to thyristor pair (top) and measured output from silicon comparator amplifier (bottom) of the hardware demonstrator of Fig. II.9, at frequency of 50 MHz.

inputs, shown in the top panel of Fig. II.10. They are synchronized to the clock driver of the thyristor pair, also shown in the top panel of Fig. II.10. The optical inputs were given to thyristor TA and TB as repetitive strings BABBBBBAAA.


The outputs of the CMOS comparator amplifier are shown in the bottom panel; and according to the Boolean description above, output from silicon should be outSiB = 1011111000. It can be seen that the output pattern matches the input

pattern, and that the NRZ between the bits functions correctly. The maximum operation frequency is 50 MHz, shown in Fig. II.10.

CCD camera

Receiver point

beam splitter

microscope objective NA = 0.6

lens reflection 90%

Emitter point(a)

Emitt er point

Receiver point(b)

Figure II.11 Experimental apparatus used for hardware demonstration in (a) and (b).

The setup used for test [Ayadi97d] is shown in Fig. II.11. A CCD camera and beam splitters are used to coincide light from emitter point with receiver point. During this process, a small adjustment of the lens reflections directs optical information towards the destination. Pulse generators create the clock driver for both emitter and receiver and were synchronized by an external trigger source.

Data has been easily translated by the two configurations shown in Fig. II.11(a) and (b). This means that the circuit operates perfectly for three dimensional data transmission.


We attribute the present overall 50 MHz limitation in these experiments to difficulties with the signal bond-wires. Future experiments on flip-chipped systems should prove higher operational frequency.

II.6 Conclusion

We have successfully demonstrated the integration of an ultrasensitive III-V detector, based on a differential pair of optical thyristors, with a dedicated novel 1-GHz CMOS comparator amplifier followed by an RS flip-flop. The maximum frequency achieved so far for the receiver is 50 MHz. Further work is under way to improve this limit to at least the frequency achievable with the thyristor pair, i.e., several hundreds of MHz [Bickel97]. Because of its small area and its high sensitivity to optical input signals, our receiver is a promising building block for CMOS-based optoelectronic circuits.


Chapter III Physics 19

Chapter III

Physics of Photodetectors in a n-well CMOS Technology

III.1 Introduction

Optoelectronic ICs are becoming increasingly important because they can provide the huge data transmission capacity needed for multimedia communications. In these systems, there is a strong demand for inexpensive and physically small photodetectors. Thus, to reduce the cost of communication systems, a fully monolithic photodetector without the need for external components or adjustment is desirable.

The integration of a photodetector in the inexpensive CMOS technology is possible by exploiting the many junction devices available in standard CMOS technology. This means that a part of the large integrated circuits will be illuminated by light. The concerned part from the integrated circuits (photodiodes) should convert the injected pulses of laser to electronic signals.

The speed limitation of standard CMOS for reception and conversion of light in the kHz range makes this CMOS technology available for image detection. The reason is that under injection of light, the diffusion of the generated carriers in the Si bulk takes a long time compared with other components with high electron mobilities such as GaAs and InP. So, a successive injection of

20 Chapter III Physics

laserpulses saturates the CMOS photoreceiver and this decreases the operating frequency.

Also, the interactions between different parts of an IC under illumination play a significant role in the functionality of the IC, one has to understand the physical phenomena.

To overcome the speed limitation of Si photoreceiver in CMOS technology, different techniques are employed in our work. The developed techniques are based on the understanding of the active mechanisms in the CMOS technology when light is injected. So, the interpretation of the mechanism occurs in the photodiode, should give us a strong capability to operate the CMOS photodiodes at high frequencies by employing the adequate techniques.

In this chapter, we recapitulate most of the equations concerning the photodiode in a standard CMOS technology, we design different photodetectors in n-well CMOS technology and interpret most of the mechanisms, then we point out one feature of optics not yet stressed: an internal phenomenon occurs under a deeply injection light in the CMOS substrate [Ayadi98c] by using the near-infrared injection (e.g., 830-nm wavelength) as a source of laser.

III.2 Photodetectors in CMOS technology

III.2.a Classic p-n photodiode

a)

light

Si

b)

I

V

I0

Iph

IdarkIlight

Voc

Figure III.1 (a) Silicon photodiode and (b) its I-V transfer.

When photon flux irradiates the junction, electron-hole pairs are generated if the photon energy exceeds the forbidden gap energy Eg = 1.12eV . The electric field of magnitude ξ sweeps the electrons from the p region to the n region and holes from the n region to the p region. This process makes the p region


positive and the n region negative, and will produce current flow in an external circuit. The voltage-current characteristic of a photodiode is shown in Fig. III.1. If there is no radiation incident on the detector, the I-V curve passes through the origin. The dark current is expressed as a function of applied voltage [Sze81] by

Idark = I0 exp

qVk T

⎛

⎝ ⎜

⎞

⎠ ⎟ −1

⎡

⎣ ⎢

⎤

⎦ ⎥

(III.1)

where I0 is the junction reverse-bias saturation current which is proportional to

the junction area, q is the magnitude of electronic charge, k is Boltzmann constant, and T is absolute temperature.

The curve is shifted downward by an amount defined as the photocurrent Iph

in the presence of radiation. This photocurrent is expressed by

Iph = ηq Φ0 Aλ

h c (III.2)

where Φ0 is the incident flux per unit area, η is the quantum efficiency, A is illuminated area, h is Plank constant, c is the speed of light in vacuum, and λ is the wavelength of light source.

As shown in Fig. III.1(b) Iph is the short-circuit current (V = 0) and is a linear

function of incident radiant flux. The total current in the presence of light is therefore expressed by

Ilight = I0 exp

qVk T

⎛

⎝ ⎜

⎞

⎠ ⎟ −1

⎡

⎣ ⎢

⎤

⎦ ⎥ − ηq Φ0 A

λh c

(III.3)

The open-circuit voltage Voc provides power under illumination. In this case the device should operate under large load resistance. The open-circuit voltage is therefore expressed as

Voc =

kTq

lnI ph + I0

I0

⎛

⎝ ⎜

⎞

⎠ ⎟

(III.4)

III.2.b N+/Psub photodetector

Monochromatic light with hν ≥ Eg penetrating in the semiconductor bulk

induces upward bandgap transistors with creation of electron-hole pairs. Inside a buried p-n junction generated carriers will be swept by the electric field, resulting in a drift current given by


Idr λ( ) = Aq Φ0 λ( )exp −α λ( )xd[ ] 1- exp −α λ( )w[ ] (III.5)

where

Φ0 λ( ) =Popt 1−Rf λ( )[ ]

Ah ν (III.6)

with α is absorption coefficient, xd is the depth of the upper edge of the buried junction, w is the junction width, Popt is the light power, Rf is the surface reflectivity, and ν is the frequency of light.

N+

subst rate P-- -

e-

e+

IN+

Idr

Idiff1

Idiff2

GateDrainSource

light

Figure III.2 Cross section of NMOS transistor showing electron-hole pairs forming in the different layers when light is injected into the source area.

Carriers generated outside the depletion region, and diffusing into the junction before they can recombine, lead to a diffusion current

Idiff λ( ) = −q Di∂Δi∂x

⎛ ⎝ ⎜ ⎞

⎠ ⎟

junction edge (III.7)

where (i = n, p), Di is diffusion coefficient of minority-carriers, and ∆i is the distribution of excess minority-carriers which is given by solving the diffusion equation that follows under boundary conditions

Di

∂2Δi∂x2

⎛

⎝ ⎜ ⎜

⎞

⎠ ⎟ ⎟ −

Δ iτ i

⎛

⎝ ⎜

⎞

⎠ ⎟ + Φ0 α exp −α x( ) = 0

(III.8)

where τi is minority-carrier lifetime.


When the flux Φ0 is absorbed across the structure, with a reverse-biased junction, several photocurrent components of different depths arise, as illustrated in Fig. III.2. The total current can be expressed by

IN + = Idiff1 +I dr1+ Idiff 2 (III.9)

This IN+ is proportional to Φ0 and depends exponentially to α which is a strong function of wavelength λ .

The relationship between this current and the junction barrier potential VN+ is given by the diode equation

VN + =

kTq

lnI N +

I0− 1

⎛

⎝ ⎜

⎞

⎠ ⎟ ≅

k Tq

lnR Popt

I0

⎛

⎝ ⎜

⎞

⎠ ⎟

(III.10)

where the responsivity is given by

R =

IN +Popt

= ηqλ

h c⎛

⎝ ⎜

⎞

⎠ ⎟

(III.11)

and the quantum efficiency by

η = 1− Rf( )1− exp −αw( )[ ] (III.12)

It is mentioned in [Gray93] that variations in voltage vbs from source to substrate of MOS transistor cause a current gmbvbs to flow from drain to source, where gmb is the body-effect transconductance.

So the advantage of this N+/Psub is that the "body-effect" [Sze81] does not

play a significant role since the substrate of the photodiode in CMOS is grounded.

III.2.c P+/n-well/Psub photodetector

P-channel transistors fabricated in an n-well CMOS process are light-sensitive when the n-well is electrically floated. Fig. III.3 shows a cross section of a p-channel MOSFET with corresponding (under illumination) energy-band diagram taken through the points C-C' in Fig. III.4.

Within a MOSFET, the photoeffect occurs primarily at the n-well and substrate n-p junction. The built-in electric field at this junction sweeps optically generated electrons into the floating n-well. This in turn causes holes to be injected across the n-well/P+ junction in an attempt to regain equilibrium. The


holes travel in one of two directions as shown in Fig. III.3. The same mechanism occurs in NMOS of Fig. III.2 by changing the notations: holes by electrons and vice versa.

P+

n-w ell

subst rate P-- -

e+

II

e-

e+I

N+ P+

e-e-

e-

C

C'

light

Figure III.3 Cross section of PMOS transistor showing electron-hole pairs forming in the different layers when light is injected into the source area. P+ diffusion layers define the drain and the source of the PMOS and N+ layer is used for n-well contact.

Ev

Ec Pote

ntia

l

Ener

gy

x

n -well P- substrat eP+

under illumination

EF

C C'

Figure III.4 Schematic band diagram for a P+/n-well/Psub available in the PMOS transistor of Fig. III.3. The arrow shows the evolution of the band energy under illumination by accumulating of photoelectrons in the n-well.

If the P+ area is small (on the order of minimum allowable size) most holes are pulled into the channel region by the two dimensional electric field, enhancing the channel current.

For larger P+ area, many electrons are injected downward across the n-well region into the p-substrate, forming a parasitic vertical bipolar junction transistor


(BJT) mode of the phototransistor operation. The n-well/P+ induced current flow Iph, in response to the accumulated electrons, increases linearly with increases in light power (every photon creating an electron causes a hole to be injected).

The relationship between this current and the junction barrier potential (n-well potential, Vn-well, which is with respect to the P+ potential) is given by the diode equation which is rearranged to form

Vn−well =

kTq

lnIphI0

− 1⎛

⎝ ⎜

⎞

⎠ ⎟ ≅

kTq

lnR Popt

I0

⎛

⎝ ⎜

⎞

⎠ ⎟

(III.13)

Note that since Iph and I0 are both proportional to junction area, the n-well

potential is independent of junction area. As the junction area increases, more electrons are generated, but they accumulate in an n-well volume that is also larger by the same factor as the junction. Thus there is no net increase in negative charge density in the n-well for a larger exposed area.

The discussion thus far has assumed a P+ area small enough to allow most holes emitted from the P+ to be captured by the channel fields. With a large P+ area, many holes will not make it to the channel before crossing the n-well into the P-substrate. Hence, a parasitic vertical p-n-p BJT phototransistor can become dominant and create a large current flow through the substrate and into the P+.

As the light power increases the current increases linearly (characteristic of a BJT photoreceiver) [Sze81]. The current Iph becomes quite large and a latch-up will occur. So there is no reason to design a large P+ area for the photoreceiver purposes, maintaining minimum size areas (60 x 60 µm2, which fits in with the optical fiber core size) will minimize the parasitic BJT effect. Also, if problems persist, operation must be confined to low-level light power conditions.

It should be noted that these MOSFETs can be rendered optically insensitive by simply supplying the n-well to a dc voltage, for example to the Vdd. Also, a

metal layer available in CMOS technology should be used over the rest of the circuit transistors (masked) to block out any illumination and then the degradation of MOSFETs performance in threshold [Bösch84] is minimized.

It is reported in [Bösch84] that under an increasing illumination, the change in effective n-well bias due to the increasing current through the substrate/n-well diode causes a change in the NMOS transistor threshold voltage VT due to "body-effect" [Sze81] (here our P+ illuminated area is the source of the PMOS transistor and the n-well is floated electrically). In consequence the change in threshold [Gray93] is expressed by


VT = VT 0 + k1 2ΦF −V n−well − 2ΦF( ) (III.14)

where the Fermi potential is given by

ΦF =

kTq

lnNn−well

ni

⎛

⎝ ⎜

⎞

⎠ ⎟ = 0.36 V (III.15)

and

k1 =toxεox

2qεsiε0

⎛

⎝ ⎜

⎞

⎠ ⎟ Nn−well

(III.16)

with the n-well impurity density (donor) Nn−well = 31016 cm−3 , the nonilluminated threshold voltage is VT0 = -0.95 V, ni is the intrinsic carrier density, and εsi is the permittivity of silicon.

Substituting (III.13) for Vn-well yields a relationship between VT and Popt which logarithmically decreases from VT0. As the threshold voltage drops, the

channel current starts to rise. It has been shown in [Bösch84] that this current also varies logarithmically with respect to light intensity. For the MOSFET linear region, the drain current ID is related to the threshold voltage VT by the equation

ID = βn VGS −VT( )V DS −V

DS2

2

⎡

⎣

⎢ ⎢

⎤

⎦

⎥ ⎥

(III.17)

where VGS and VDS are gate-to-source and drain-to-source voltages, respectively.

If (III.14) is substituted for VT, a relation between the drain current and the incident light power is formed

(III.18)

ID = βn VGS −VT 0 − k1 2ΦF −KTq

ln RPopt I0( )− 2 ΦF⎛

⎝ ⎜

⎞

⎠ ⎟

⎡

⎣ ⎢

⎤

⎦ ⎥ VDS −

VDS2

2

⎧ ⎨ ⎪

⎩ ⎪

⎫ ⎬ ⎪

⎭ ⎪

ID will vary approximately as ln(Popt) when all other terms are held constant. This theoretical relationship predicts the drain current's response to light. So the dependence of the drain current to the light injection degrades the MOSFET


performances and increases the chances that latch-up will occur at high injection of light.

III.2.d Monolithic color detection

The identification of color light plays a significant role in the demultiplexing of multi-wavelength optical fiber. The demultiplexing can be of use in optical communications [Mos97] where an incoming packet of binary optical data needs to be identified and routed to a specific electronic output channel, as shown in Fig. III.5. The capability of the optical fiber for guiding multi-wavelengths and the capability of the photodetector for discriminating them have a good impact in optoelectronic networking. The optical bus will be realized simply by a multi-wavelength optical fiber and a photodetector demultiplexer CMOS circuit.

λ1, λ2 , ..., λn

out1

.

.

.

out2

fiber demul tipl exerPD

outn

Figure III.5 Configuration of the optoelectronic photoreceiver demultiplexer.

Employing a buried double p-n junction (BDJ) structure implemented with a standard CMOS technology, monolithic wavelengths can be identified. This technique is based on the strong dependence of silicon absorption depth on the incident light wavelength. The absorption coefficient varies sharply in the visible region, i.e., the exponential decrease in depth of generated photocarriers is distinctly related to the wavelength.

The structure of the photodetector is proposed by [Lu96] and is presented in Fig. III.6. The use of two buried p-n junctions can split the silicon bulk into several layers where photocurrent components can be collected and contribute to a shallow current IP+ and a deep current In-well, as shown in Fig. III.6. The ratio of photocurrents allows the determination of the wavelength, i.e., the injected color of light.

When the flux Φ0 is absorbed across a BDJ structure, where two buried junctions are reverse biased, several photocurrent components of different depths arise [Lu96]. Through the two electrodes A and B shown in Fig. III.6, two


external currents IP+ and (IP+ + In-well) can be measured. Based on equations III.5 - III.8, currents IP+ and In-well are given by

IP + = Idiff 3 + Idr2 + Idiff 4 (III.19)

In−well = Idiff 5 + Idr3 + Idiff 6 (III.20)

n-w ell

substrat e P-- -

N+P+

light

IP+

Id r2

Idiff3

Idi ff4

In-w ell

Id r3

Idiff5

Idiff6

Vp+

Vn-well

AIP+ (Ip++In-w ell)A

A B

Figure III.6 Device cross-section of the BDJ photodetector for color light detection.

Both IP+ and In-well are proportional to Φ0 , but the ratio In-well/IP+ depends only on the absorption coefficient α which is a strong function of wavelength. Calculating the ratio In-well/IP+ against wavelengths shows a monotonous increase in the visible range (solid curve in Fig. III.7, after [Lu96]). This curve can be used to discriminate monochromatic colors: different ratios of measured photocurrents correspond to different wavelengths. Qualitatively such a result can be predicted since, e.g., blue light is absorbed more shallowly than red light, causing much weaker photocurrent component in deeper layers. As a result the ratio is smaller.

Numerical analysis done by E. Y. Lu [Lu96] shows that a photon flux penetration across a buried p-n junction will lead to a photocurrent which has a smooth peak against wavelengths. The peak response wavelength increases when increasing the depth of the junction. In the case of a BDJ device consisting of diffusion-well-substrate layers in a CMOS process, two photocurrents IP+ and In-well are peaked in the blue and the red regions, respectively, [Lu96]. Providing the two peaks are located near both visible limits, the ratio In-well/IP+ keeps rising with wavelength over the visible range.


Under operating condition, Vp+ > Vn-well > 0, and for a source light with a spectral bandwidth, the resulting ratio In-well/IP+ is given by [Lu96]

r =In−well λ( )dλ∫

IP + λ( )dλ∫=

I n−wellIP+

(III.21)

In the case of a single peak with a narrow band, both mean values IP + and In−well can be replaced approximately by IP+ and In-well at peak wavelength, respectively. As a result the ratio is not altered in comparison with the case of monochromatic light, as simulated and measured by [Lu96] in Fig. III.7. The use of the ratio for detection of wavelengths presents an excellent agreement between computed and measured results. This ratio is not affected by the fluctuation of penetrating photon flux. This fluctuation is due to the reflection spectrum Rf λ( ) dependence, resulting from the surface passivation SiO2 layer

on the top surface of the chip.

Figure III.7 Calculated and measured ratio In-well/IP+, a monochromator was used as a wavelength-variable light source. After [Lu96].

This demonstration confirms the capability of the BDJ implemented in CMOS technology for the wavelength detection in the range [400-nm, 1000-nm] or in term of color (spectrum) from violet to red.


III.2.e Vertical pnp BJT photodetector

To overcome the problem of body-effect and latch-up, one solution is to build a proper p-n-p bipolar junction transistor (BJT) in standard CMOS technology. The P+/n-well/Psub photodetector discussed previously was modified in Fig.

III.8. To achieve a p-n-p bipolar transistor in CMOS technology, the P+ diffusion layer acts as the emitter, the n-well defines the base, the P- substrate is a common collector, and the N+ used for n-well contact. The well area (the base) of transistor Q is enlarged for detection of input beams.

n-well

substrat e P-- -

N+

e-

e+I

P+

Q

e+

e+

II

light

Figure III.8 Cross section of the vertical pnp BJT available in CMOS technology. Light injected into the n-well creates electron-hole pairs in the n-well and P- substrate layers. Electrons diffused from the substrate to the n-well causes event I. The answer of the P+ in event II is depicted by the vertical thick arrow. The secondary effect, which is shown by the horizontal thin arrow, is minimized by isolating the n-well from other transistors.

As shown in the cross section in Fig. III.8, BJT-CMOS transistor Q is defined as three different layers P+/n-well/P-. The photoeffect occurs primarily at the n-well and substrate n-p junction. The built-in electric field at this junction sweeps optically generated electrons into the floating n-well, as it is the case in the PMOS structure discussed previously. This in turn causes holes to be injected across the n-well/P+ junction in an attempt to regain equilibrium. The holes travel in one of the two directions horizontal and vertical. They are pulled into the two directions by the two dimensional electric field.

Yet, the horizontal current in this structure does not affect the performances of the photodiode. Because the P+ layer is too thin (about 0.3 µm in this technology), most holes are injected downward across the n-well region into the P- substrate, forming a vertical bipolar junction transistor BJT mode of operation.


III.3 Deeply illuminating MOS effect (DIME)

III.3.a Introduction

The photodetectors need to be fairly thin to obtain the true absorption depth, especially, for samples with depth equal to the absorption depth Ln. Certainly, if the sample is thick enough, as it is the case in the projected samples available in CMOS technology with a substrate of about 600 µm, special precaution must be followed to extract the true absorption depth and diffusion time with an appropriate theoretical analysis. If such analysis is not used, then an erroneous diffusion time may be obtained [Ayadi98c]. The experiment accompanies the theoretical analysis to agree the introduced techniques in the control of the photodetectors.

III.3.b Transversal diffusion effect

np (x) exp −x Ln( )

Ln0

np0

np(0)

x

Figure III.9 Generated photocarriers (electrons) versus depth penetration light in the P- substrate. Light arrives to the substrate at x = 0 and enters through it until the total absorption, after [Sze81].

It is necessary to point out an important effect that occurs during operation under an increasing illumination. It is well known that the absorption of incident light from the vacuum into the different layers takes the curve shown in Fig. III.9 [Sze81]. Light absorption in different layers of the semiconductor produces hole-electron pairs. The differential equation is expressed by

Dn∂2np

∂x 2 −np − np0

τn= 0

(III.22)

with


Dn =kTq

⎛

⎝ ⎜

⎞

⎠ ⎟ μn (III.23)

Ln = Dn τn (III.24)

where np is the minority-carrier density, np0 is the thermal-equilibrium minority-carrier density, and Ln is the diffusion length.

The light intensity decreases until the attenuation by an increase in depth x. So the boundary conditions are

np x = 0( ) = np 0( )= Cte

np x → ∞( ) = np0

⎧ ⎨ ⎪

⎩ ⎪

(III.25)

the solution of np x( ) is given by

np x( ) = n p0 + np 0( )− np0[ ]exp −x Ln( ) (III.26)

the absorption coefficient can be deduced from Fig. III.9 and expressed by

α =1

Ln (III.27)

This absorption coefficient is considered as one of the important parameters in photodetector conception. For practical applications, researchers build a p-i-n photodiode by using special masks in silicon. Because p-i-n photodiode presents a high response speed by the fact the intrinsic i-layer width is equal to Ln. Since the majority of photons are absorbed in the intrinsic layer, the generated carriers in this i-layer are all collected and those generated outside i-layer are neglected. The transit time across this depleted i-layer is customary to have the half of the modulation period. So the photoresponse is optimized and the p-i-n photodiode is therefore operated at its near maximum frequency [Lucovsky64].

However, these previous performances of p-i-n photodiode are not valid in our projected p-n photodetectors in CMOS technology, because there is the effect of diffusion of carriers created in the different layers and specially in the substrate. The diffusion time can lower the response speed of the photodetectors. Light is usually considered to reach the 1 α depth [Chen97]. So for the injected λ = 830nm laser, the internal quantum efficiency η is close to 100 % and the absorption depth is 1 α = 10μm [Sze81].


III.3.c Photocarrier diffusion time analysis

By introducing the absorption depth in the following equation gives the diffusion time that the created minority photocarriers (electrons) in the substrate should take to reach the top layer

τdiff =Lsub2

Dn

(III.28)

In the model presented in Fig. III.10, the depth of the P+ layer is 300 nm, the depth of the n-well is 2.2 µm, and the depth of the substrate is about 600 µm. So the mechanism of diffusion time of photocarriers occurs in four different stages: diffusion through the affected substrate τdiff2 ,Lsub( ), transit across the n-well/substrate depletion region τt 2 ,wl 2 + wu2( ), diffusion through the upper edge wu2 of the n-well/substrate depletion layer to the lower edge wl1 of the P+/n-well depletion layer τdiff1,Ln−well( ), and finally transit across the P+/n-well depletion layer τt 1,wl1 +wu1( ). The mechanism is shown in Fig. III.10.

n-well

P+

substrate P --

e+e-

e+e-

e+e-

e+e-τdiff2

τdiff1

τt2

τt1

w u2

w l2

w u1w l1

light

Figure III.10 Deeply illuminating MOS effect in the pnp BJT. Electrons created in the substrate diffuse toward the n-well and take a long time (τdiff2 + τt2), while electrons from

n-well diffuse toward the P+ diffusion in a shorter time (τdiff1 + τt1).

The depletion width [Sze81] is given by

w =2 εsi

qNA + NDNA ND

⎛

⎝ ⎜

⎞

⎠ ⎟ Vbi +V( )

(III.29)


and the transit time through the depletion layer is given by

τt =wvs

(III.30)

where V is the applied voltage to the junction, Vbi is the built-in potential, NA and ND are the acceptor and donor impurities, respectively, and vs is the saturation

drift velocity (107 cm/s). The doping numerical values are given in table III.1.

Table III.1 Minority carrier lifetime and doping numerical values in 0.7-µm 5-V n-well CMOS technology.

P+, N+ n-well P- substrate

doping 1020cm−3 3 ⋅1016 cm−3

5 ⋅1015cm−3

lifetime ≤10ns 1,10[ ]μs 10,100[ ]μs

resistance 85 , 60 Ω/ 1300 Ω/ 9 - 15 Ω.cm (*)

(*) resistivity

We find wl2 = 0.62 µm, wu2 = 0.195 µm, wl1 = 0.2 µm, wu1 = 3.43 nm, and then Ln-well = 1.505 µm and Lsub = 7.18 µm. So by introducing these numerical

values in their appropriate equations (III.28) and (III.30), we can deduce the total required time for the generated electrons in the bottom of the device (at Ln = 10

µm deep for the injected 830-nm laser [Sze81]) to reach the P+ top layer. We find τdiff2 = 13.3 ns, τt2 = 0.08 ps, τdiff1 = 0.58 ns, τt1 = 0.02 ps. The total

diffusion time is therefore about 13.88 ns, which means that the maximum operating frequency of the photoreceiver is 72.05 MHz.

III.3.d Interpretation

The above analysis allows us to operate the photodiode at a frequency in the range of 70 MHz, when it is not true. For today's Si photodiode available in CMOS technology, the operated frequency is less than 2 MHz [Ni97, D.-Castro97]. The decrease in frequency is not essentially due to CMOS sensor pipelining the photodiode but due to an active physical phenomenon in the body of the photodiode when light is injected. This phenomenon has not been reported and resolved yet.

It is generally found that for Si photodiode the photocarriers deeply generated over the 1/α deep are neglected, which is faulty. The reasons for the discrepancies (concerning the maximum operating frequencies discussed previously) are fundamental and are not due to a deficiency of the


measurement. Since the diffusion time depends directly on the affected depth by light, special precaution must be followed to extract the true absorption depth and diffusion time. Since semiconductor affected by light always contains some generated charges in diffusion, this mechanism of photocarrier moving is always active under injection.

Ln x

Sn1 %

np0

np(0)

np(x)

LDIME

SDIME

Figure III.11 DIME phenomenon results in the deep substrate. The estimation of the depth LDIME affected by light is 4.6.Ln and the photocarrier density is approximately 35 % from the total, as depicted by SDIME in the graph.

The Fig. III.9 is re-projected in Fig. III.11 with more concentration in the DIME phenomena. As we can see from Fig. III.11, the mentioned area SDIME is

situated between Ln and LDIME . The numerical value of LDIME is equal 4.6.Ln and calculated by taking np x( ) equal to 1 % from the generated charges at the

origin, meaning np LDIME( )= 1% np 0( )− np0( ).

The generated charges in the area SDIME is calculated and approximated to

be 35 % from the total generated charge. Thus the high number of photocarriers generated in the SDIME must be taken into account. If we insert the new estimation of LDIME instead of Ln in the appropriate equations (III.28) - (III.30), we find Ld(sub) = 43.18 µm and we can conclude a more realistic diffusion time. We find therefore τdiff2 = 0.48 µs and then the total diffusion time

is about 0.48 µs, which means that the maximum operating frequency of the photoreceiver is 2.08 MHz.

The true operating frequency of the photodiode is achieved by taking into account the DIME phenomena. The maximum allowed frequency is therefore


2.08 MHz and not 72.05 MHz in this technology. It is also demonstrated by measurement.

To expose the photoreceiver continually to the light decreases considerably the operating frequency. This phenomenon is the same as when exposing the human eye directly to the sunlight for a while, and it will take a long time for the return to the normal functioning.

Three techniques are exploited to overcome the frequency limitation of the silicon photoreceivers: (1) by injecting short lightpulse delay into the photodetector in order to leave the maximum of time for the photocarrier diffusion current generated in the n-well/substrate photodiode; (2) by sensoring by connecting the photodiode to a refresh circuit (sequentially connection e.g. to a dc voltage) in order to operate the photodiode dynamically or differentially; (3) by biasing by applying a reverse voltage in order to extend deep the n-well/substrate depletion-layer into the p-type substrate, and then more photocarriers are generated in the depletion layer and accelerated by the intense electric field.

III.4 Measurement

III.4.a Setup considerations

To demonstrate the internal phenomena into the BJT-CMOS structure, we have measured the amplified generated photocurrent from the photodiode by an addition of an amplifier CMOS circuit (Fig. III.12) which is integrated on chip together with the photodiode. External resistors are connected to a probe, as shown in Fig. III.12.

BJT-CMOS Q is connected to an amplifier. The n-well of Q is exposed to pulses of λ = 830nm⇔ hν = 1.49eV( ) laser-diode. The photodiode is controlled

by an external clock to connect the n-well sequentially to a dc voltage. The current Iph is amplified by the amplifier by a factor of 8300 in Iout . The read-out

probing pad of resistor R2 of 100 Ω is connected through 50-Ω cabling to an infinite resistor R1 of 1 MΩ input of an oscilloscope and allows electrical read-out of the state.

Almost all the setup has been used by G. Bickel to perform other measurements on GaAs in [Bickel97].


R1R2

probe

pad

amp

Vdd

clockIout

e-

e+

Iph

n-well

subst rate P--

N + P+

Q

light

Figure III.12 The proposed schematic used for measuring the DIME. Resistors R1 and R2 and the probe shown at the right are external from the integrated device shown at the left. R1 is the input resistor of the measuring oscilloscope.

clock:

lightpulses:

Figure III 13 Timing diagram of the proposed circuit in Fig. III.12.

The timing diagram of the circuit is shown in Fig. 10. The circuit configuration allows us the possibility to measure the photodiode without refreshing the photodiode by simply grounding the clock.

III.4.b Dynamic operation

Fig. III.14 depicts the dynamic operation of the proposed circuit in Fig. III.12. The photodiode (n-well of Q) was exposed to a laserpulse sequence of "000101011111" with "1" means a lightpulse was injected and "0" no light was injected. To grasp the DIME phenomena into the photodiode, the frequency of this experiment was kept low at 100 kHz to minimize the effect of the probe.

As shown in the first panel from the top of Fig. III.14, the injected light was an optical-pulse of 5-ns pulsewidth and an external energy of 275-aJ/pulse during the following two measurements.


During the first measurement, the clock was grounded. In the second panel of Fig. III.14, the amplified generated photocurrent was therefore observed by the external circuit of R1 and R2.

When lightpulse is injected, the photodiode reacts by generating a pulse of photocurrent. This pulse of photocurrent takes time to return-to-zero (RZ) due to the diffusion time into the affected substrate of the photodiode.

light

pul

ses

(a.u

.)

150

100

50

0

curr

ent

(x10

-6 A

)

200x10-6

150100500time (s)

4

2

0

volta

ge (

V)

150

100

50

0

curr

ent

(x10

-6 A

)

Figure III.14 Experiments at low frequency of 100 kHz. From top: incident laserpulses on the n-well in the first panel, the next panel is the read-out current Iamp at the pad point when the clock is grounded during the first experiment. For the second experiment, the clock is applied to the photodiode in the third panel, and the read-out current Iamp at the pad point is shown in the forth panel.


After a successive injection of lightpulse, the diffusion time affects considerably the RZ of the photocurrent pulses as depicted by arrows in the second panel of Fig. III.14. The higher the injected light the more the diffusion time takes place until the saturation when the RZ disappears.

In the second measurement, the clock of 0- to 5-V was applied as shown in the third panel from the top of Fig. III.14. The lightpulse was set into the same configuration as below. In the forth panel of Fig. III.14, the RZ of the generated photocurrent pulses was settled. The reason for that is that during the half-cycle clock at 5-V, the n-well is reverse biased to a dc voltage and the n-well/substrate depletion-layer is widely depleted.

We find that by biasing the n-well to Vdd = 5 V, wl2 = 1.6 µm and wu2 = 0.5

µm. Thus the buried depletion-layer is more than doubled at 2.1 µm. The majority of the generated photocarriers which are generated during the previous half-cycle (Fig. III.13), at 0-V, are swept-out from the substrate. The junction n-well/P+ is reverse-biased which triggers off the BJT Q. So Iout is turned off

abruptly.

When the half-cycle clock at 0-V clock begins, an incident 5-ns pulsewidth of light is immediately injected. About 10 % of photocurrents are generated in the buried depletion-layer (n-well/substrate) and immediately accelerated by the existing strong electric field. During the rest of the half-cycle, most of the generated photoelectrons in the substrate will probably reach this doubled buried depletion-layer and participate in the generation of photocurrent Iph.

We can conclude that with this technique the clock is used for refreshing the photodiode after each injection of light, and this will perform significantly the CMOS photodetector towards high operating frequencies.

III.4.c Physics and photonic analysis

To see the limit of this clocked photodiode, we have measured the circuit shown in Fig. III.12 under high injection. Because the dynamic range of the clocked photodiode is wide enough, the limitation at high light injection at frequency of 100 kHz was not reached. The laser diode must be triggered by a high pulse of current over the capability of the pulsegenerator. By increasing the operating frequency at 500 kHz and by injecting a 100-ns pulsewidth of light, the limit was observed and plotted in Fig. III.15.

The repetitive train of "000101011111" of optical pulses is respected as shown in the second panel from the top of Fig. III.15. The answer of the clocked photodetector by pulses of currents is shown in the third panel of Fig. III.15. Bit-


errors are created under an injection of an external input light of 1.15 pJ/pulse: current pulses shown by "I" are generated without injection of light and correspond to the forth "0" (from the right of the repetitive train); current pulses shown by "II" are bit-error generated and correspond to the fifth "0"; current pulses shown by "III" are bit-error generated and correspond to the first "0".

4

2

0

volta

ge (

V)

150

100

50

0curr

ent

(x10

-6 A

)

50x10-6

403020100

III

IIIIIIII

I

lase

r (a

.u.)

Figure III.15 Bit-errors are generated at high light injection. From the top: the applied clock voltage at 500 kHz, incident laserpulses on the n-well, read-out current at the pad point shows the generated erroneous current pulses in different configurations: after one light pulse in I and II and after a succession of laserpulses in III. The amplitudes of these bit-errors differ.

The interpretation of this measurement is based on the Stevenson-Keyes method [Stevenson59]. When the sample is illuminated with light and no electric field ξ is applied (because it is concentrated into the depletion layer and quasi absent somewhere else), the equation controlling the minority carrier density in the semiconductor material [Sze81] (electrons in the P- substrate for example) is rearranged to form

∂np∂t

= G −np − np0

τn (III.31)


At steady state ∂np ∂t = 0 and if at t = 0, the light is turned off then there is

no generation, G = 0, and the boundary conditions are

np t = 0( ) = np0 + τn G

np t = ∞( ) = np0

⎧ ⎨ ⎪

⎩ ⎪

(III.32)

the solution of (III.31) is given by

np( t ) = np0 + τnGexp −t τn( ) (III.33)

where G is the electron-hole photogeneration rate for the given wavelength light at a distance x from the semiconductor front surface and expressed by

G = Φ0α exp −α x( ) (III.34)

Table III.1 presents the minority carrier lifetime in the used 0.7-µm 5-V n-well CMOS technology.

Equation (III.33) is plotted in Fig. III.16. At a certain point and after the affectation of the semiconductor by a lightpulse, the decay of minority carriers is exponentially [Sze81].

τ n

np0

n (0)p

t

exp −t τn( )pn (t)

0

Figure III.16 Decay of minority photocarriers (electrons) by time in the P- substrate. A laserpulse excites the substrate at t = 0, after [Sze81].

The representation of the generated photocarriers inserted in Fig. III.16 can help to understand the evolution of the amplitude with the time. The portion of the generated photoelectrons is given by


′ n p t( ) = n p(t ) − np0 = τn G exp −t τn( ) (III.35)

and the attenuation of the amplitude after a number m of cycle T0 can be expressed by a portion from the maximum amplitude ′ n p 0( ). This attenuation is independent from G and given by exp −mT 0 τn( ). So the amplitude of the erroneous pulse "I" is expressed by ′ n p 0( )exp −T0 τn( ), where ′ n p 0( ) is the

maximum amplitude of the generated amplified photocurrent that corresponds to the first "1" (from the right of the repetitive train).

The maximum amplitude of the erroneous pulse "II" is given by the addition of

′ n p 0( )exp −3T 0 τn( ) of the first "1" to ′ n p 0( )exp −T0 τn( ) of the second "1" of

the train. During measurement all laserpulses have the same power. It is shown in Fig. III.15 that the seventh "1" of the train generates an erroneous pulse "III" with higher amplitude than in "I" and "II", as depicted in Fig. III.15. This is due to the accumulation of the photocarriers in the substrate after a successive injection of laserpulses.

In general, the influence of the previous successive m lightpulses on the actual state can be expressed by

Δ ′ n p = ′ n p 0( ) exp −i T0 τn( )

i=1

m∑

⎛

⎝ ⎜

⎞

⎠ ⎟

(III.36)

A total sweep-out of the photocarriers from the substrate means a Δ ′ n p = 0 :

this is the case of the efficient CMOS photoreceiver with an operating frequency in the GHz range.

III.4.d Horizontal diffusion effect

The evolution of the generated carriers after an injection of lightpulse is known as Haynes-Shockley experiment and is reported in [Haynes51]. The transport equation in the substrate by setting G = 0, ξ = 0 and considering that np x,t( ) = np0 for x → ∞ is expressed by

np( x ,t ) = np0 +

∂np02 πDnt

exp −x2

4Dnt−

tτn

⎛

⎝ ⎜ ⎜

⎞

⎠ ⎟ ⎟

(III.37)

where ∂np0 is the excess photocarrier density created at x = 0 by the radiative

generation [Schroder97].


t1

t2

x

t1 < t2

np0

pn (x,t)

0

Figure III.17 Diffusion of the initial generated photocarrier by a light pulse at x = 0 and at t = 0. The amplitude is reduced continually from t1 to t2 and the curve spread takes more space at t2 due to the diffusion and the recombination of the photocarriers in the substrate, after [Sze81].

The plot of equation (III.37) is shown in Fig. III.17. The maximum amplitude of each curve is situated at the origin of the injected laserpulse at x = 0 and t > 0, because ξ ≅ 0 in the substrate (with resistivity 9 - 15 Ω.cm, see table III.1), and is determined by

np( 0,t )max = np0 +∂np0

2 πDntexp −

tτn

⎛

⎝ ⎜

⎞

⎠ ⎟

(III.38)

When many openwindow photodiodes exist in a single chip as shown in Fig. III.18, the interaction between photodiodes under illumination is due to the diffusion of the generated photocarriers away from the initial position of the injected lightpulse. If a laserpulse takes place into the photodetector 1, as shown in Fig. III.18, the minority photoelectrons in the substrate diffuse slowly by the diffusion time τn from event I to event II.

Many electrons slip under the n-well of the photodetector 2 and diffuse vertically towards this n-well, as shown in Fig. III.18. This results in a change of the local substrate neutrality of the photodetector 2. Dynamically, this local substrate is a floating voltage due to this vertical diffusion. The injection of laserpulses into the photodetector 2 will cause a quick saturation by the accumulation of photoelectrons in its local substrate.

To overcome this problem, all photoreceivers should be refreshed after each clock-cycle.


n-well

hνphotodetector 1 photodetector 2 photodetector 3

P- substrate

x

n (x,t)p

e-e-

e-

diff

usio

nI

II

sem

icon

duct

or d

epth

Figure III.18 An injection of a laserpulse is given on the n-well of the photodetector 1. The diffusion horizontally of the generated photocarriers (electrons) in the substrate, from the event I at t to the event II at t + ∆t, affects the neutrality of the substrate under the n-well of the photodetector 2 and diffuses vertically toward the n-well of the photodetector 2. This interaction affects the performance of the photodetector 2.

The more the photodetector 3 is located far from the photodetector 1 the less the interaction between them, as depicted in Fig. III.18. We conclude here that during the design of photodetectors, the distance between photodiodes should be considered to minimize the horizontal diffusion effect.

The determination of the minimum distance between two photodiodes is not possible without approximation, because the number of the previous injected laserpulses during the lifetime of 100 µs can not be defined. Dynamically, these laserpulses change as shown in Fig. III.18 and cause continual perturbations.

If we assume that the operating frequency of the photodetectors is fixed at 100 MHz and the number of the previous laserpulses is at its maximum of 10000 (during the lifetime of 100 µs) but only few of them are considered, because the photocarriers attenuate exponentially as shown in Fig. III.17. Also, if the estimated minimum distance, between photodetector 1 and photodetector 2 of Fig. III.18, is defined and corresponded to the existence of only 1 % from the maximum amplitude of the generated photocarriers by the previous injection, as depicted in Fig. III.18 by e- under photodetector 2: according to (III.37) and (III.38), we find a minimum distance between photoreceivers of 26.76 µm that must be strictly respected.


To make sure that the estimation is valid and the interaction between photodiodes is annulled, we extend the calculated minimum distance of 26.76 µm to an estimated value of 50 µm.

III.5 Conclusion

We discussed different photodetectors available in n-well CMOS technology. Different physical equations are collected in this chapter. Most of the phenomena are explained and different internal mechanisms are detailed.

An internal phenomenon is active in the substrate when light is injected. This phenomenon is explained and demonstrated for the first time. The interactions between different parts of the IC under illumination have a negative impact on the functionality of the IC. Some techniques are used to avoid the performance degradation of the photodiodes.

This study is a base necessary for building preferment photoreceivers in CMOS technology.


Chapter IV Double-beam monolithic CMOS photoreceiver 47

Chapter IV

Double-Beam Monolithic CMOS Photoreceiver

IV.1 Introduction

Faster compound semiconductor devices other than Si material has been strongly developed during these last years [Karlsen95, Woodward96b] for the realization of monolithic photoreceiver. The reason is that Si material presents a low absorption coefficient, meaning a large absorption depth for the given wavelengths below 1.1 µm. Si material is however transparent above this value. Thus a long sweep-out time proportional to the wavelength will limit the Si device speed. The yield in productivity of Si based-material is very high compared to that of GaAs based-material, which makes Si more attractive.

Also, the design of a photoreceiver in Si based-material will resolve the cost of the OEIC receiver, and a challenge work should be if we use the inexpensive standard CMOS technology without introducing any special mask.

In this section, pn junctions available in standard CMOS were used as photodiodes. To compensate for their expected lower detector quantum efficiency we included differential operation with competition. In CMOS, differential operation with competition can be provided by a sense-amplifier. A sense-amplifier is a small dual-inverter system [Van-Noije95], dissipating no dc-power, and serving in DRAMs (with thousands of them operating simultaneously and in parallel [Kawahara93]) to detect the small signals (some millivolts) on bit-

48 Chapter IV Double-beam monolithic CMOS photoreceiver

lines and to convert these signals to mere digital levels within a few nanoseconds. A draw-back of the sense-amplifier is that it has to be triggered. The use of an optical receiver based on a sense-amplifier is therefore limited to synchronous detection of light.

In this chapter we report about the first receiver based on the sense-amplifier with integrated photodetectors in 0.7-µm standard CMOS at high operating frequencies [Ayadi97a, Ayadi97b] and [Schaffer98].

IV.2 Design and operation

IV.2.a Circuit design and simulation

bl-b

out

LTCH

RST

M1

M2 M3

M6

M7

Vdd

LTCH

h νhν

bl

out

M5M4

Figure IV.1 Schematic of the optoelectronic sense-amplifier photoreceiver, the light is injected sequentially into the enlarged drain areas either of the NMOS M4 and M5 or of the PMOS M2 and M3.

The sense-amplifier circuit with integrated photodiodes is shown in Fig. IV.1. This circuit is known as conventional sense-amplifier (CSA). Two versions were conceived: a PMOS- and an NMOS-version. In the PMOS version (Fig. IV.1), the drains of the p-MOSFETs M2 and M3 are enlarged to 15 x 15 µm2 to serve as photodiodes; conversely in the NMOS version, the drains of the n-MOSFETs M4 and M5 serve as photodiodes. An indicative cross-section for the enlarged drains is given in Fig. IV.2. The complementary pairs M2 + M4 and M3 + M5 operate as a latch. Transistor M1 and M7 connect and disconnect the power supply, and M6 can bring the voltage difference on the integrated photodiodes to zero. Others setups of sense-amplifiers can also be used. The inputs LTCH


and RST were controlled separately for measuring purposes. Integrating a few more transistors allows the detector of Fig. IV.1 to be triggered by a single digital input.

The operation of the circuit works in three phases. Fig. IV.2 shows the timing of the applied pulses RST and LTCH, and of the light input.

LIG

HT

INJE

CTI

ON

pha

se

RST:

LTCH:

light in put pulse:

RES

ET

phas

e

LATC

HIN

G p

hase

Figure IV.2 Timing diagram with the different phases.

For the RESET phase, transistors M1 and M7 are switched off (LTCH = ‘0’) and M6 is switched ON (RST = ‘1’). Outputs bl and bl-b are thus shorted and brought to the floating level of roughly 2.5 V.

For the subsequent LIGHT INJECTION phase, M1 and M7 are kept off (LTCH = ‘0’) but M6 is opened (RST = ‘0’) such that the outputs are free to change voltage. Light is injected upon one of the two drains (M4 or M5) of the NMOS detector, or on one of the two drains (M2 or M3) of the PMOS detector. This leads to a small disequilibrium on nodes bl and bl-b.

For the final LATCHING phase transistors M1 and M7 are switched ON (LTCH = ‘1’) while M6 is kept open (RST = ‘0’). The circuit is pushed from the metastable situation (with the small disequilibrium) to a stable digital state [Van-Noije95, Sarpeshkar91].

The Hspice-simulated response of the circuit is shown in Fig. IV.3. In this simulation, the light input was simulated by a current source of 25 µA. The transition to the stable state with digital voltage levels can be seen to take about 3 ns.


Figure IV.3 Simulation of the sense-amplifier. Two controlling inputs determine the state. The digital voltage levels make the output suitable for further on-chip use. Transistor geometries: M1-M5 (W/L = 2 µm/0.7 µm), M6 (W/L = 3 µm/0.7 µm), M7 (W/L = 1 µm/0.7 µm).

The circuit was designed [Ayadi97b] by using a single-poly double-metal 0.7-µm 5-V n-well CMOS technology. The cell layout is presented in Fig. IV.4. The symmetric left-right top-down sides were respected during design layout stage to achieve a proper circuit functionality. A minimum mismatch in MOSFET parameters can create unsuccessful sensing due to a mismatch in threshold voltage. In this case the sense-amplifier amplifies the input signal in the wrong direction [Sarpershkar91, Van-Noije95].

A mismatch can always happen in our CSA when the transistor geometric parameters (W, L) of the left side inverter (M2, M4) are different from these of the right side inverter (M3, M5) of the sense-amplifier. These mismatchs disturb the equal drive capability and cause an unsuccessful sensing. The sense-amplifier will sense in the wrong direction as shown in Fig. IV.5.

In this figure the W/L of the transistors are sized for an unbalanced pull-up and pull-down left/right sides. The sense-amplifier is not sensitive to the inputs.


At t = 0 the perfectly balanced sense-amplifier with zero differential voltage at 2.5 V would just start conducting. The left side pull-up more than that of the right side, the input writing data pushes the left side to the 0-V state, as shown in Fig. IV.5 from t = 2 ns to t = 6 ns. Because of the anomaly in the circuit, the sense-amplifier drives always the left side to the 5-V final state, as shown in Fig. IV.5 at t > 6 ns.

M2

M1

M3

M5M6

M4

M7 Active layer

Figure IV.4 Layout of the PMOS version of the circuit. The areas (active layers in the figure) define the enlarged drains of the p-MOSFETs (M2, M3); for the NMOS version, the areas define the enlarged drains of the n-MOSFETs (M4, M5).

5.0

4.0

3.0

2.0

1.0

0.0

volta

ges

(V)

1614121086420

time (x10-9

s)

right side

left sideunsuccessful sensing

Figure IV.5 Simulation of the unmatched sense-amplifier. Transistor M4 is sized with W/L = 2 µm/3 µm. All other transistors are kept as in Fig. VI.3. The left side of the circuit has a strong pull-up capability. As a consequence, the final latch state will always be logical (left side = 1, right side = 0).


If the generated layout parasitic capacitances of M2 and M4 match these of M4 and M5, respectively, by a careful design, the sense-amplifier should sense properly. The more the designed sense-amplifier is symmetric the high is the sensitivity.

IV.2.b Small-signal analysis

Cd

gm.V1

Cd

gm.V2

Rd

V1 V2

Rd

Figure IV.6 Small-signal equivalent circuit for the conventional CMOS sense-amplifier CSA.

The small-signal equivalent circuit of our CSA is drawn in Fig. IV.6, in which Cd is the equivalent capacitance at the output nodes of the sense-amplifier including the Miller capacitance from Cgd, the diffusion capacitances, and the bit-line capacitance Cbl. For the conventional sense-amplifier case, Cbl is the dominant portion of Cd so Cd ≅ Cbl . The transconductances of the p-channel and n-channel devices have been lumped into a single equivalent gm, and Rd

includes the parallel combination of the output resistances of both the n- and p-channel devices [Blalock91].

The expression for the loop gain T is found to be

T =gm Rd

1+ sRd Cbl( )⎡

⎣ ⎢

⎤

⎦ ⎥

2

(IV.1)

The gain of each of the inverters has a single dominant pole determined by Rd and the bit-line capacitance Cbl. Note that for this sense-amplifier, the large bit-line capacitance interacts with the large output impedance Rd . Table IV.1

presents the key device parameters from this process that were used for calculations and computer simulation. M2-M4 have a W/L = 8/0.7. M1, M6 and M7 have a W/L = 15/0.7, 12/0.7 and 4/0.7, respectively.

Based upon these device parameters, the dominant pole for this sense-amplifier is located at 1.3 MHz. For the given Cbl = 0.6 pF, the loop gain

expression leads to a ac small-signal gain-bandwidth (GBW) of approximately 263 MHz according to the formula


GBW =

gmCbl

(IV.2)

Table IV.1 Hspice Key Model Parameter.

Parameter NMOS PMOS Unit

Vto 0.75 -0.95 V

Kp 9.547 3.209 10-5 A/V2

Gamma 0.751 0.531 V1/2

CGS0 3.1 3.1 10-10 F/m

CGD0 2.2 2.2 10-10 F/m

Phi 0.798 0.762 V

Tox 170 170 Å

Nsub 70 35 1015 cm-3

Ld 0.1 0.06 µm

Cj 5 6 10-4 F/m2

Lambda 3.6 4.2 10-2 V-1

Fig. IV.7 shows the Hspice simulated small-signal frequency response of the sense-amplifier. The simulated GBW product of the sense-amplifier is very close to that predicted by the previous first-order analysis. The GBW is directly proportional to the bit-line capacitance. So by increasing Cbl the circuit takes

more time to reach its two stable states 0 and 5-V.

A challenge sense-amplifier receiver was reported for use as a receiver circuit by A. Z. Shang in [Shang96]. The circuit is a 9 MOSFETS clamped-bit-line sense-amplifier (CBLSA) [Blalock92]. This circuit exhibits a response time independent of Cbl . In case of a high Cbl , the performance of the CBLSA will

not be affected. Even when the sense-amplifier is flip-chipped by another material used for detection and modulation of a specific wavelength λ of laser [Woodward96b], the Cbl will take more high value due to technology limitation.

In this case the CBLSA is a good candidate [Woodward96b].

The schematic, the functionality and the small-signal analysis of the CGLSA circuit are reproduced in appendices 2 for comparison with our CSA circuit. Fig. IV.7 shows that the ratio of the gain bandwidth (GBW) product of the two sense-


amplifiers is about GBWCBLSA GBWCSA = 2.8 . So that the CBLSA should be about one-third of order of magnitude faster than that of our CSA. The reported CBLSA receiver in [Shang96] was only simulated at frequency of 333 MHz, and the input light was replaced by two ideal input current pulses.

However, the experimental measurements on the CBLSA were not achieved by the authors.

50

40

30

20

10

0

-10

loop

gai

n (d

B)

1010

109

108

107

106

105

104

103

102

101

100

frequency

CBLSA our CSA

Figure IV.7 Small signal gain versus frequency for CSA and CBLSA sense-amplifiers.

The time response of our CSA is carried out by Hspice simulator. In this simulation the Cbl takes the typical value 0.6 pF of a classic RAM's bit-line

capacitance, which is imposed by the forced data storage bit-line (electrical writing) external circuit into the sense-amplifier. An extension to 1.2 pF affects considerably the speed response of the CSA.

In Fig. IV.8, the voltage difference Vd between the voltages (Vbl, Vbl-b) at the

output nodes of the sense-amplifier shows that the CSA takes 3.29 ns for the given Cbl = 0.6 pF and 6.65 ns if we double the Cbl . The CBLSA time response produced in appendices 2 gives only 1.24 ns for both Cbl values. A ratio of about 2.65 between the two sense-amplifiers for the given Cbl = 0.6 pF is

consistent with the GBW analysis.

Hereby, the increase of the bit-line capacitance Cbl by the introduction of

other material on the CMOS sense-amplifier circuit for detection of light decreases considerably the speed response of the conventional sense-amplifier. So our approach by injecting directly the light into the sense-amplifier limits the Cbl to its minimum value.


5.0

4.0

3.0

2.0

1.0

0.0

volta

ges

(V)

2520151050

time (x10-9

s)

Vbl

Vbl-b

Vd

VRST

Cbl = 0.6 pF Cbl = 1.2 pF

Figure IV.8 Time response of our CSA for both cases: when it is loaded by a Cbl = 0.6 pF and 1.2 pF and generates 1-V in 3.29 ns and 6.65 ns, respectively, as it is depicted by the voltage difference signals.

IV.3 Measurements and photonic interpretations

The system proposed in Fig. IV.1 was designed and fabricated in a standard 0.7 µm 5 V n-well CMOS process. The photograph of the sense-amplifier is shown in Fig. IV.9. The drains' depths are about 300 nm, and the n-well is about 2.2 µm. To measure the digital outputs, outside the chip, output buffers were foreseen. Their capacitive output load during tests was about 5 pF. The effective area without the output buffers is about 55 x 24 µm2.

Taking into account the effect of the passivation nitride layer on top of the optical windows, the amount of light effectively reaching the silicon is about 75 % of the external applied light due to reflection at the interface [Ayadi97a].


2 drains (photo-diodes)

2 buffers15 µm

Figure IV.9 Photograph of the sense-amplifier with integrated photodiodes under test: light is incident on the photodiodes. Large output drivers make the received bits measurable outside the chip.

IV.3.a NMOS version

In the NMOS version, electrons generated within approximately 2.7 micron from the junction (Fig. IV.10) have the time to diffuse to the junction within 2 nanosecond. On the other hand, the absorption depth of the 830-nm light is about 10 micron [Sze81]. This means that about 27 % of the light generated in the semiconductor diffuses to the junction.

The latch was experimentally measured to operate correctly with an external optical input of 176 fJ (at 180 MHz), corresponding to 36 fJ effectively charging the drain junction [Ayadi97a].

e+N+ N+

substrat e P -

hν

e-

- -

Figure IV.10 (NMOS version) Cross-section of NMOS transistor whereby the enlarged drain area serves as a photodiode: carriers are generated at the N+/substrate junction and around it, electrons drifting and diffusing towards the drain, holes drifting and diffusing towards the substrate.


Optical inputs were given on the left (L) and the right (R) drain junction of M4 and M5 in the order RRLLRL. Fig. IV.11 show the measured outputs of the NMOS latch operating at its maximum frequency of 180 MHz, or at the bitrate of 180 Mbit/s. During these experiments, the light input was given as 2 nanosecond pulses of 830-nm laser diodes.

5

4

3

2

1

0

-1

outp

ut le

ft si

de (V

)

5

4

3

2

1

0

-11009080706050403020100

time (x10-9

s)

outp

ut r

ight

side

(V)

Figure IV.11 Measured output signals at maximum operating frequency: the NMOS version operated at 180 Mbit/s.

IV.3.b PMOS version

In the PMOS version, only half of the light generated carriers in the 2.2-micron deep n-well can diffuse to the drain junction (Fig. IV.12), the other half going towards the substrate. This corresponds to about 11 % of the light generated carriers. The experimentally externally required 802 fJ thus correspond to an effective 66 fJ [Ayadi97a].


-

N-well

P+

5V

P+

subs trate P-

N+

-

e+e+

e-

e -

hν

Figure IV.12 (PMOS version) Cross-section of PMOS transistor whereby the enlarged drain area serves as a photodiode: carriers are generated at the P+/n-well and n-well/substrate junctions and around them, holes drifting and diffusing towards the drain and the substrate, electrons drifting and diffusing towards the n-well.

6

5

4

3

2

1

0

outp

ut le

ft si

de (V

)

5

4

3

2

1

0

140120100806040200

time (x10-9

s)

outp

ut r

ight

side

(V)

Figure IV.13 Measured output signals at maximum operating frequency: the PMOS version operated at 120 Mbit/s.

Optical inputs were given on the left (L) and the right (R) drain junction of M2 and M3 in the order RRLLRL. Fig. IV.13 shows the PMOS version operating at maximum frequency, 120 MHz. During these experiments, the light input was given as 2 nanosecond pulses of 830-nm laser diodes.


IV.3.c Photonic analysis

In both the NMOS and the PMOS version, the carriers collected on the illuminated drain junction change the voltage on that drain by a small amount. The approximate capacitance of the n+ junction collecting the 830-nm light is 120 fF, meaning that 36 fJ of light charges the junction by 201 mV. In the PMOS detector, the effective 66 fJ of light charges the 160 fF junction by 264 mV. We conclude that the charging of the junctions is very similar in both cases, and the difference in external required light input is essentially due to the difference in absorption due to the presence of a well. During the LATCH phase, these small voltages are amplified to the logic levels as shown in Figs IV.3, IV.11, and IV.13.

The exact dissipation of the receiver could not be measured separate from the buffers used to transfer the received information outside the chip. However the capacitances of the affected nodes of the sense-amplifier have similar values as the nodes from a standard cell CMOS logic gate or flip-flop, operating with the same voltage swing. Therefore, the receiver/converter is expected to show similar power dissipation behavior as a CMOS logic gate or flip-flop.

To improve the sensitivity, the wavelength of the incident light can be decreased. Absorption lengths will decrease and detector quantum efficiency will rise accordingly. A better understanding of the sense-amplifier operation in combination with the photodiodes should allow to improve detectable voltage differences. Sensing a voltage difference of at least ten times smaller than the higher deduced 200 mV should become feasible, increasing the sensitivity of the receiver even further.

IV.4 Conclusion

We presented a novel monolithic optoelectronic receiver in standard CMOS based on a sense-amplifier. The first experiments show 180 Mbit/s and 176 fJ operation for the better of two tested versions. The optical sensitivity is expected to be improved considerably in future optimized versions and by using light with shorter wavelength. Its low-cost fabrication in standard CMOS, its compactness, its speed, its projected improved sensitivity and its low-power operation make this receiver an interesting candidate for use in parallel optical interconnects between -chips.


Chapter V Single-beam monolithic CMOS photoreceiver 61

Chapter V

Single-Beam Monolithic CMOS Photoreceiver

V.1 Introduction

The previous photoreceiver is differential. It works with double input light: one at left side and the other at right side, sequentially. The quit difficult task is the realization of a Si photoreceiver works with a single input light at high frequency by using standard CMOS technology. A great deal of effort has been devoted to developing the perform photoreceiver. Measurement has been achieved at 100 MHz operating frequency with only an external input light of 13.3 fF (-18.8 dBm/beam).

More details of the photoreceiver strategy are revealed in the following description. The schematic and the operation of the new single-beam photoreceiver are detailed also in follow.

V.2 Detailed photoreceiver design and analysis

V.2.a Photoreceiver architecture

To achieve quick response and high sensitivity, we have used a synchronized photoreceiver that includes three principal stages [Ayadi98a], as shown in Fig. V.1. The detector stage consists of a CMOS photodiode (PD) that

62 Chapter V Single-beam monolithic CMOS photoreceiver

is connected directly to a preamplifier or even included within. The integration of a photodiode into the preamplifier is possible by exploiting the many junction devices available in CMOS technology [Ayadi97a, Ayadi98a]. To improve sensitivity, a very-low-noise preamplifier is strongly desired. In such a CMOS preamplifier design, high current gain and low noise characteristics are required. A bipolar junction transistor (BJT) implemented in CMOS technology is a great device to meet these requirements [Vittoz83, Pan89, Zeitzoff85].

To synchronize the photoreceiver, an external clock signal is applied to the preamplifier. The clock is required to control the external incoming input light and provides a good stability to the photoreceiver. When the clock is applied, the preamplifier should be insensitive to the incoming input light and then insensitive to the generated photocurrent. The preamplifier stage can be rendered optically insensitive by simply connecting the detector area to a dc voltage [Ayadi98a]. This approach is extremely important for the dynamic operation of the photodiode, and it provides a quick response.

Output voltage

CL

BuffPost- amp

Pre- amp

PDInput light

Current amplified

Analog voltage

Digital voltage

Clock

refresh

Figure V.1 The proposed dynamic photoreceiver architecture. Clock synchronizer is applied to the detector stage to insure quick response.

A post-amplifier stage is needed for the conversion of the amplified photocurrent generated by the previous stage to a voltage signal. A high gain post-amplifier is required to establish an analog signal. It is preferable to generate a wide swing analog signal to make signal processing easier by the next stage [Gray93].

To drive an external large load capacitance, a buffer stage is required. This buffer completes the analog signal processing and generates the output voltage in its digital format.


V.2.b Preamplifier circuit

The schematic of the preamplifier is shown in Fig. V.2. The circuit is designed in n-well CMOS technology and the implementation of a vertical p-n-p BJT is therefore available. The photoDarlington [Sze81] is used for the detection of the incoming input light [Espejo94] and for the amplification of the generated photocurrent.

As shown in Fig. V.2, the basic clocked photoDarlington contains two p-n-p vertical BJTs and two NMOS switches [Ayadi98a]. Transistors Q1 and Q2 are connected to achieve a Darlington configuration. M8 and M9 are used for refreshing the photoDarlington and are controlled by an external signal clock.

clock

M9 M8

Q1

Q2

ID

l igh t

VD

Figure V.2 CMOS preamplifier circuit, base-collector junction of the BJT Q2 acts as photodetector.

P+N+

n-well

P+

substrate P -- -

N+

e-

e+

light

Q1Q2

Iphe+

Figure V.3 (Q1, Q2) Darlington configuration available in CMOS technology.

The cross-section of the photoDarlington and its layout are drawn in Fig. V.3 and Fig. V.4. To achieve a p-n-p bipolar transistor in CMOS technology, the EMBED "Equation" \* mergeformat P + diffusion layer acts as an emitter, the n-well defines the base, the P − substrate is the common collector, and the N + is


used for n-well trap contact. The well area (base), AB2, of transistor Q2 is enlarged for detection of input beams.

M9 M8

BaseQ2

Q1Emitter

St rap contact

Figure V.4 Layout of the preamplifier, the empty area of Q2 is specified for the injected input light.

The applied clock is a repetitive 0-, 5-V of pulses and light should be injected at the beginning of the 0-V. The operation of the preamplifier can be explained physically as follows:

When the clock voltage is high, M8 and M9 of Fig. V.2 turn on. Hence, the base of Q2 is connected to the base and the emitter of Q1 and approaches Vdd − VT 1 = 4.1V . The base-collector junction of Q2 remains at a reverse-bias

of about 3.4 V (more details in Hspice simulation). This reverse bias voltage causes the depletion region to extend deep into the p-type substrate (Fig. V.3) by 1.8 µm instead of the 0.8 µm without a reverse-bias [Sze81].

Under this condition, photocarriers existing in the n-well/substrate depletion-layer are accelerated by the electric field into the depletion edges. Electrons are collected in the n-well and holes in the substrate.

According to [Ayadi97a] and at clock-frequency of 100 MHz, 73 % of the photoelectrons generated in the substrate are collected in the n-well [Ayadi98b]. This portion becomes 88 %, if the laser-pulse delay takes only 1-ns of the previous half-cycle in order to leave the maximum of time for the photocarrier diffusion current. So most of the photoelectrons are swept out from the substrate, and only 12 % escape the refreshing phase [Ayadi98b].


When the clock is low, M8 and M9 are off. An incoming input light through the base of Q2 triggers the transistor action. A photocurrent is therefore generated by the photodiode well-substrate junction of Q2 and is expressed by

Iph = ηq Φ0 AB2

λhc

(V.1)

where η is quantum efficiency given by

η = 1− Rf( )1− exp −αwd( )[ ] (V.2)

where Φ0 is the incident photon flux per unit area, λ is the wavelength of light source, h is Planck’s constant, c is the speed of light, α is the absorption coefficient (1000 cm-1), Rf is the surface reflectivity, and wd is the width of the n-

well/substrate depletion layer of Q2.

As more electrons are collected in the n-well, the base voltage decreases and the depletion region continues to collapse. Every photon creating an electron in the base of Q2 causes a hole to be injected from the emitter into the base of Q2 in an attempt to regain equilibrium [Ayadi98a]. Thus, the base-emitter junction induces current IE 2 which increases linearly with the input light power Popt . The relationship between Popt (in µW) and the junction barrier potential VB2 (n-well potential) is given by the diode equation

VB2 =

kTq

lnIE2I0

− 1⎛

⎝ ⎜

⎞

⎠ ⎟ ≅

kTq

lnR Popt

I0

⎛

⎝ ⎜

⎞

⎠ ⎟

(V.3)

where I0 is the junction reverse-bias saturation current and R is the responsivity given by

R = IE 2 Popt = ηq λ h c (V.4)

Note that since IE 2 and I0 are both proportional to the junction area, the n-

well potential is independent of the junction area. As the junction area increases, more electrons are generated, but they accumulate in an n-well volume that is also larger by the same factor as the junction. Thus there is no net increase in negative charge density in the n-well for a larger exposed area. This area independence was confirmed experimentally [Ayadi98a].

V.2.c Post-amplifier circuit

The CMOS post-amplifier is a current-mirror comparator, as shown in Fig. V.5, and it has been designed to convert into voltage the current generated by


the photoDarlington. Since the input transistor M1 is diode connected, the input impedance of the post-amplifier is about 1 gm1 which is typically the lowest resistance possible for MOS device without using feedback. A class-A current source inverter (M4, M7) is implemented. Its small-signal output resistance is given by

Rout = 1 gds4 + gds 7( ) (V.5)

and it is driven from a low resistance source of approximately 1 gm6 . gm and gds are the transconductance and the output conductance, respectively, of the corresponding MOS transistor number which is indicated by an index.

M2M1Vbias M4

Vdd

Vout

M6 M7

Iin

+ -

Vin

CL

Figure V.5 Post-amplifier circuit loaded by an ideal current source.

In this post-amplifier circuit, the output dc level is determined by the selection of device characteristics, such as FET size and a common source FET setting. The maximal voltage level is restricted by the power supply level Vdd (M7 is off). Hence the high limited level, Vout high( ), is represented by

Vout high( ) ≅Vdd (V.6)

The minimal voltage level is found by assuming that M7 is in the nonsaturation region. Here, the gate of M7 is taken to Vdd , the low limited voltage level, Vout low( ), is then represented by


(V.7)

Vout low( ) = Vdd −VT 7( ) 1− 1−′ K 4W 4 L7′ K 7W 7 L4

⎛

⎝ ⎜

⎞

⎠ ⎟

Vdd −Vbias − VT 4Vdd −VT 7

⎛

⎝ ⎜

⎞

⎠ ⎟

2⎡

⎣

⎢ ⎢

⎤

⎦

⎥ ⎥

1 2⎧

⎨ ⎪

⎩ ⎪

⎫

⎬ ⎪

⎭ ⎪

where W and L denote the device width and length, respectively. VT is the threshold voltage. ′ K is the transconductance parameter. All of them are indexed by the corresponding MOS transistor number. Vbias is the bias voltage applied to the gate of M4.

V.3 Small-signal analysis

The small signal behavior of the post-amplifier shown in Fig. V.5 is very important in order to compare the performance of the post-amplifier in the two following cases: (1) when it is loaded by an ideal current source; and (2) when it is loaded by the preamplifier of Fig. V.2.

The small-signal transconductances of M1-M7, and their output conductances are noted gmi and gdsi , respectively, with i = 1,. .. 7 . Cgs , Cgd , and Cbd are, respectively, the gate-to-source, -to-drain and substrate-to-drain device capacitances. gm Qi( ) , g π Qi( ) and go Qi( ) are, respectively, the small-

signal transconductances, input conductances and output conductances, and are indexed by their appropriate bipolar transistors Q1 and Q2.

The use of a symbolic small-signal simulator like ISAAC [Gielen94] yields a quite complicated open-loop transfer function ℜ s( )= Vout Iin , with a second-

order numerator and a third-order denominator, which are too lengthy to be usefully reproduced here. However the complete numerical small-signal analysis and curves generated by ISAAC give a good insight.

V.3.a Ideal analysis

To achieve analytical relationships between the pole-zeros and the small-signal device parameters: the post-amplifier is presented by a simplified circuit and its small-signal model [Liu82] circuit is shown in Fig. V.6 and Fig. V.7. Furthermore, some simplifications introduced in the generated expressions overcome the complexity of the full small-signal equations. The relationship between the parameters shown in Fig. V.7 and the parameters of the circuit is reveled in table V.1.


Vbias M4

Vdd

Vout

M7

V0 I0 R0

CL

Figure V.6 Simplified post-amplifier circuit for small signal analysis.

+

I0C0

Cgd7

C out RoutR0

gm7.V0

VoutV0

+

Figure V.7 Simplified small signal model of the post-amplifier.

Table V.1 The equivalent expression of the simplified parameters of Fig. V.7 as a function of the device transconductances gm and conductances gds of M1-M7, and the capacitance coupling gate-to-source Cgs , gate-to-drain Cgd , and bulk-to-drain Cbd of the output stage M4 and M7.

Rout =1

gds4 + gds7 (V.8)

R0 =1

gm6 + gds6 + gds2≅

1gm6

(V.9)

C0 ≅ Cgs 7 (V.10)

Cout = Cbd7 + Cbd 4 + Cgd 7 + CL (V.11)

V0Vin

= −gm 2gm6

(V.12)


I0Iin

= −gm2

gm1+ gds1≅ −

gm 2gm1

(V.13)

VinIin

≅1

gm1 (V.14)

The transimpedance gain ℜ s( ) can be expressed as follows

ℜ s( )=VoutI in

≅ −ℜ01− s z1

1+ As + Bs2 (V.15)

where ℜ0 , z1, A , and B are given in table V.2 as functions of the small-signal device parameters.

Table V.2 Analytical expression of the transfer function characteristics of Fig. V.7 as a function of gm , gds of M1-M7 and Cgs , Cgd , and Cbd of the output stage M4 and M7.

ℜ0 =gm2 gm 7

gm1gm6 gds4 + gds7( ) (V.16)

A =Cgs7 + Cgd 7

gm6+

Cgd 7 + Cgd 4 + Cbd 7 +Cbd 4gds 4 + gds7

+gm 7Cgd7

gm6 gds4 + gds7( )(V.17)

B =Cgs7Cgd 7 + Cgs7 + Cgd 7( )Cgd 4 +Cbd7 + Cbd4( )

gm6 gds4 + gds7( ) (V.18)

The open-loop transfer function ℜ s( ) allows an easy expressions of the zero z1 and the two poles p1 and p2 of the post-amplifier in these following expressions

z1 =gm 7Cgd 7

(V.19)

p1 =−1A

≅−gm6 gds4 + gds7( )

gm6 Cgd7 + Cgd4 + Cbd7 + Cbd 4 + CL( )+ gm7 Cgd7 (V.20)


p2 =−AB

≅ −gm 6 Cgd 7 + Cgd 4 + Cbd 7 + Cbd 4 +CL( )+ gm7 Cgd 7

Cgs7 Cgd 7 + Cgs7 + Cgd7( ) Cgd 4 + Cbd 7 +Cbd 4 +CL( )

(V.21)

The zero z1 occurs in the right half-plane due to the feed-forward path through Cgd 7. The pole p1 is more dominant than p2 as they are expressed as the typical ratio of gds C and gm C , respectively, and gm is always larger than of gds . The numerical analysis of the comparator in 0.7-µm 5-V n-well CMOS technology is done by ISAAC and is depicted in Fig. V.8.

The transimpedance gain at low frequency ℜ0 is about 162 dBΩ. The first pole of the post-amplifier with a capacitive load CL = 1pF is located at 1 kHz, the second pole is located at 2 MHz. The phase of the open-loop transimpedance gain of the post-amplifier amounts to 42 º at the cut off frequency of 100 MHz.

150

100

50

0

-50

tran

sim

peda

nce

gain

(dB

)

108

107

106

105

104

103

102

101

100

frequency (Hz)

-150

-100

-50

0

50

100

150

gain

phase

Post-amplifier Post-amplifier & Darlington

phas

e (º

)

Figure V.8 ISAAC simulated phase and gain of the post-amplifier leaded by the discussed two cases: an ideal current source that is presented by the square marks; and (Q1, Q2) Darlington that is presented by the circle marks.

V.3.b Entire analysis

The post-amplifier is loaded by a p-n-p Common-Collector-Common-Collector cascade (Q1, Q2) Darlington configuration of Fig. V.2 by replacing Vin and Iin of Fig. V.5 by VD and ID , respectively. Since the characteristics of the circuit change due to the input impedance of the post-amplifier is now the equivalent output impedance of the (Q1, Q2) Darlington. This output impedance


can be approximated by 1 gm Q1( ) which is in parallel with 1 gm1. The

approximation is done by assuming that the small-signal output resistance of the common collector configuration goes to infinity and then go Q1( ) and go Q 2( ) are

kept to zero [Gray93].

The output stage M4 and M7 is driven from a lower equivalent resistance at the gate of M7 but does not have any effect on the performance of the circuit. Hence M7 is driven from the low resistance source of about 1 gm6 . Consequently, there is no change in the location of the pole-zeros of the circuit. The voltage gain of (Q1, Q2) is close to unity by the low load impedance, 1 gm1. Hence the post-amplifier is driven by the emitter current of Q1 which is β + 1( )2 Ib2 , where Ib2 is the input base current of Q2.

The ratio I0 Iin expressed in table V.1, becomes the ratio of I0 by Ib2 and is expressed by

I0Ib2

= −gm 2gm Q2( )

gπ Q1( ) gπ Q2( )

⎛

⎝ ⎜ ⎜

⎞

⎠ ⎟ ⎟

(V.22)

Consequently, ℜ0 raises and is given by

ℜ0 ≅gm Q1( ) gm 2 gm7

gπ Q1( ) gπ Q2( )gm6 gds4 + gds7( ) (V.23)

The numerical analysis of the comparator loaded by the (Q1, Q2) Darlington in 0.7-µm 5-V n-well CMOS technology is also done by ISAAC and depicted in Fig. V.8. The transimpedance gain at low frequency is increased up to 178 dBΩ. The locations of p1 and p2 are kept without change. At 100 MHz, the phase of the open-loop transimpedance gain of this circuit amounts to 129 º with gain of 51 dB as shown in Fig. V.8. Thus the performance of the proposed post-amplifier is not degraded when it is loaded by the (Q1, Q2) Darlington.

Since the gates of M8 and M9 are connected to an external large signal clock, the addition of these transistors to the previous circuit does not make any significant change as M8 and M9 contribute solely with their drain-source impedances rds8 and rds9 , respectively. These are seen in parallel with smaller r π Q1( ) and r π Q2( ) of Q1 and Q2, respectively. Hence, the small-signal

analysis performed earlier of the post-amplifier loaded by (Q1, Q2) Darlington does not change by adding M8 and M9 to the circuit. This is confirmed by ISAAC.


V.4 Operational principle

V.4.a Photoreceiver circuit

The schematic of the synchronized photoreceiver [Ayadi98a] is shown in Fig. V.9. The load capacitance CL is the capacitance of the external pad and package. It is estimated at 5 pF. The post-amplifier of M1-M7 is therefore buffered by two levels of complementary CMOS inverters. The input capacitance of the buffer stage is typically between 50 fF and 100 fF.

Since the base of Q2 is exposed to the light, photoDarlington current ID is

induced and given by ID = β + 1( )2 I ph , where β is the BJT current-gain. This current ID is reflected back from the photoDarlington and it is mirrored and amplified by M2 in Iamp. The current Iamp will be compared with a reference bias current by M3-M7 [Current94]. This results in a RZ format. The gate of M7 is connected to the diode-connected M6 to replicate Iamp by M7 in Irep. A reference current is established by M3 and M5, and it is mirrored by M4 to establish the threshold current Ith and the bias voltage Vbias.

M2M1

Vp ad

CL= 5pF

M4

M5

M3

Vdd

M6 M7

VoutIamp

Ith

VampIrep

M9 M8

clock

Q1

Q2

VD

VE2VB2li ght Ib1

Vbias

ID

Figure V.9 The proposed CMOS synchronized photoreceiver circuit.

The output current is defined as the difference of the two drain currents Irep and Ith . The current-mirror comparator provides the two logical output voltages Vout : a logical high output voltage for Irep less than Ith , and a logical low output voltage for Irep higher than Ith .


In this 0.7-µm 5-V n-well CMOS technology, β = 22.5 and the generated photocurrent is rearranged to be reflected in this design by Irep = 177509Iph .

More details about the operation are revealed in the following Hspice simulated response of the circuit.

V.4.b Photonic analysis

The minimum optical light input was simulated by current pulses, Iinj , of 400-

nA amplitude (200 nA average) as shown in the bottom panel of Fig. V.10. This current is generated by an ideal current source connected to the base of Q2. This would correspond in practice to -34 dBm average external power injected per beam or 16 fJ/beam external pulse energy [Ayadi98a].

With real photoreceiver, we deducted 35 fJ/beam external pulse energy. This means that the simulated circuit is more as sensitive than a real circuit, probably due to the fact that the simulator did not take into account the considerable diffusion delay of the generated photocarriers to reach the n-well/substrate depletion layer compared to the modulation period [Ayadi98a].

During measurement, the light pulse delay should take a few ns from the corresponding half-cycle (here when clock is at its low state) in case to leave the maximum of time to the photocarrier diffusion current generated in the n-well/substrate photodiode. Thus, the minimum input light can be located easily by simulation at the given frequency, and it is a very important step in the design procedure of the photoreceiver circuit.

The proposed photoreceiver has two new features in its clocked photoDarlington configuration. The first feature is that Q1 and Q2 are controlled by M8 and M9 rather than a classic Darlington structure. This clocked photoDarlington synchronizes the photoreceiver circuit. The second is the pull-up of the base voltage of the phototransistor Q2 junction to auto-reverse its base-collector when the clock is high, instead of the conventionally used phototransistor in [Espejo94].

The auto-reverse strong voltage removes the excess charge at the base of Q2 during the first half-cycle, to just reduce the diffusion delay of the generated photocarriers to reach the junction as will be explained in the following discussion.


V.5 Simulations and discussion

V.5.a Hspice simulation

The Hspice simulation shown in Fig. V.10 represents three and a half cycles. Input current is injected in the first and the third cycle to see how the circuit performs when the injection is missing in the second cycle. Before the high-low clock transition arrives the base and emitter voltages of Q1 and Q2 are held between 3.4 V and 3.9 V [Ayadi98a]. The reason for that can be understood by the following sequence of events.

Figure V.10 Hspice simulation of the photoreceiver, the circuit is clocked by a 0 to 5-V swing signal. Insert of the bottom panel: depicts a weak base current of Q1 from t = 40 ns to t = 60 ns.


V.5.b From t = 20 ns to 40 ns

After the high-low clock transition takes place (see Fig. V.10 from t = 20 ns to t = 40 ns) an input current pulse of 20-ns is injected and charges the base of Q2 and turns Q1 and Q2 on, as depicted by Iinj in the bottom panel of Fig. V.10. This charge is confined in the n-well and forces Q2 into saturation, so that VD goes gradually toward VCEsat Q 2( ) +VBEon Q1( ) ≅ 0.1+ 0.7 volt . The simulated

waveforms in the top panel of Fig. V.10 show how the curves of VB2 , VE 2 and VD are separated by VBEon . The current ID is at its maximum value and is mirrored in Iamp , so that the voltage Vamp in the (M2, M6) branch is pulled up

as shown in the middle panel of Fig. V.10.

The voltage Vout , shown in the middle panel, is the discharge of the input capacitance of the buffer through M7 by the difference of the two drain currents of M4 and M7 when Irep becomes higher than Ith [Current94]. Since Vout

reaches its low voltage level (corresponding to the low injection), the buffer stage inscribes a pulse of 0-V by discharging the 5-pF load capacitance CL , as depicted by Vpad in the middle panel of Fig. V.10.

V.5.c From t = 40 ns to 60 ns

When the low-high transition of the clock arrives (from t = 40 ns to t = 42 ns), VB2 , VE 2 and VD are pulled up, due to the charging of the base-collector capacitances of Q1 and Q2 by a current through M1, M8 and M9 to just turn Q1 and Q2 off (until VBE 2 = VBE1 = 0 V ). From t = 44 ns, no current flows (the drains and sources of M8 and M9 are coupled together), so that VD increases toward Vdd − VT 1 until it is clamped at VE 2 +VBEon at t = 52 ns. At this

moment Q1 turns on and a weak reverse current flows through M1 and M8 and charges the base of Q1 as depicted by Ib1 in the insert of the bottom panel of Fig. V.10. VD will reach 3.9 V. Ib1 is weak because it is controlled by M8 whose drain and source voltages are close to the saturation level.

V.5.d From t = 60 ns to 80 ns

When the high-low transition of the clock arrives (from t = 60 ns to t = 62 ns), VB2 , VE 2 and VD are pulled down due to the capacitive coupling between the clock node and VB2 , VE 2, and VD nodes. These parasitic capacitances are generated by the designed layout of the circuit and are depicted in Fig. V.11 by Ci and C j with i = 1,... 4 and j = 5, 6. C1-C4 are the gate-to-source and gate-

to-drain capacitances and are determined by the overlap capacitance and the channel capacitance in the linear region, and expressed by


Ci = W LCov

L+

Cox2

⎛ ⎝ ⎜ ⎞

⎠ ⎟ (V.24)

while C5 and C6 are derived from the base areas and their connections to the substrate.

clock

C5

C4C1 C2 C3

C6

M9 M8

Q1Q2

IFT

Figure V.11 Redistribution of the generated parasitic capacitances that cause clock feedthrough problem: overlap capacitances C1, ... C4 of M8 and M9, and the generated layout base-to-collector capacitance C5 of Q2 and C6 of Q1.

So when the clock begins to fall abruptly, an unavoidable feedthrough current IFT is induced [Song93, Kinget97], and expressed [Ayadi98a] by

IFT =Ci

2

Ci + C j

⎛

⎝ ⎜ ⎜

⎞

⎠ ⎟ ⎟

V S +VTΤt

⎛

⎝ ⎜

⎞

⎠ ⎟

(V.25)

where VS and VT are the source and threshold voltages, respectively, of the concerned NMOS switch, and Τt is the clock fall transition time from VS +VT to 0-V. Note that IFT changes direction during the rising clock from 0-V to VS +VT .

A peak of 500 nA base current of Q1 crosses both coupling capacitances: source-gate C2 of M9 and drain-gate C3 of M8, as drawn in the bottom panel by Ib1 of Fig. V.10. This results in a peak of about 12 µA emitter current for Q1 due to the Q1 transistor action. From then VBEon is maintained between VD and VE 2.

Under the transition, Vout is perturbed negatively and reduces the swing voltage at the input of the buffer to ∆Vout = 2.32 V, as depicted in the middle

panel of Fig. V.10.


After the high-low transition takes place (from t = 62 ns to t = 80 ns), M8 and M9 are off. There is no path anymore for the minority carrier base charge of Q1 to leak out. The charge remains confined in the well and maintains the emitter current of Q1, so that VD increases slightly to its final value separated from VE 2 by the value of VBEon . Finally VD will reach 3.9 V.

Note that while VE 2 increases, the base-emitter voltage of Q2 will reach VBEon (normally, it takes 45 ns to reach VBEon ), yet, Q2 remains off because its base current is zero.

V.5.e From t = 80 ns to 100 ns

The switching-on of M8 and M9 under the low-high clock transition (from t = 80 ns to 82 ns) pulls up VB2 , VE 2 and VD . A reverse current flows through M1 and charges the base-collector capacitances of Q1 and Q2 through M8 and M9, so that the remaining minority charge from the previous sequence ceases to exist. Q1 turns off and Q2 remains off. The current at node VD is attenuated after charging. VD increases more rapidly than during the previous sequence which was characterized by a high emitter current caused by the transistor action of Q1 at node VD .

From t = 82 ns to t = 100 ns, VD continues to increase toward 3.9 V. M9 is in the triode regime and M8 enters saturation. Q1 and Q2 remain off because their base-emitter voltages are less than VBEon . The 0.2 V difference between the 4.1 V and the 3.9 V is most likely due to leakage current in Q1.

V.5.f Interpretation

It is noticed that during the first half-cycle clock at 5-V, M8 and M9 are switched on and connect the base voltage VB2 and the emitter voltage VE 2 of Q2 to the drain voltage VD of M1 at the voltage of Vdd − VT 1 .

Three events result from this state: (1) the Darlington is off and no current flows. The photoreceiver does not change its state under an erroneous incoming input light injection (confirmed experimentally); (2) most of the excess photocarriers generated during the previous cycle in the inner transistor Q2 layers are swept and the photoDarlington is prepared for the next incoming light pulse; (3) VB2 rises to a voltage greater than 3.4 V and hence wd is kept at 1.8

µm.

The current-input-voltage-output propagation delay is typically 10 ns. The power dissipated in this first version photoreceiver is about 2.5 mW (4 dBm).


V.6 Noise switching circuit affects

As demonstrated in the previous description, a switching circuit (M8, M9) is needed to connect VB2 to a reverse voltage for refreshing after injection phase. It increases the maximum operation frequency significantly. This electrical switching circuit however causes electrical noise and large parasitic capacitance effects. The electrical noise degrades the photoreceiver performances in sensitivity and operating frequency.

Since there is no gain in the refresh circuit (M8, M9), thermal noise will play a very important role in the stability of the base signals. When a clock is applied to the base-collector capacitors C5 and C6 of Q2 and Q1, respectively, they are seen in parallel. Their top plates are charged to the base voltage and their bottom plates are connected to the collector voltage. These capacitances introduce a KT C thermal noise which limits the bandwidth of the circuit.

The sampled switched-gate noise contributes KT C/ / ≅ 64.4 µV rms at

room temperature and a noise density of 6.44 nV/ Hz for a bandwidth above 100 MHz, where C/ / is the equivalent capacitance of the parallel connection of C5 and C6 shown in Fig. V.11.

To suppress electrical noise and parasitic capacitances caused by the switching circuit to a minimum, and reduce clock feedthrough noise, first, the photoreceiver has been operated without light injection. Experience plotted in Fig. V.12 shows that clock feedthrough affects strongly the output signal and is considered here the dominant source of noise. The top panel of Fig. V.12 depicts the output voltage of the photoreceiver under power supply and the clock is grounded, while the bottom panel depicts the noisy output voltage when clock is applied.

Since feedthrough affects ∆Vout considerably, we propose to integrate the

smallest possible transistors M8 and M9 to achieve the smallest switched capacitors which should be in the order of a few fF with a careful layout, and the larger n-well areas of the Q1 and Q2 bases in order to achieve large switched capacitors which should be in the order of a few 100-fF.

With this approach, the feedthrough current is reduced by minimizing each capacitance plate of C1 -C4 and carriers are minimized and will not disturb the large capacitance C5 and C6 . Hence ∆Vout is maintained as wide as possible.

The base areas of Q1 and Q2 have to be large, because Q2 determines the detectability of light beams that occupy a considerable area of the optical fiber core diameter, of about 50 µm, used for the optical interconnection on the base


of Q2. Also the contact area is required for the connection of the base of Q1 to M8, M9 and Q2 as shown in Fig. V.2.

5

4

3

2

1

0

outp

ut (

V)

5

4

3

2

1

0

1.00.80.60.40.20.0

time (x10-6

s)

out

put

(V)

clo

ck (

V)

Figure V.12 Experimental improvement of the dominant feedthrough. (a) output voltage of the photoreceiver under power supply only and (b) noisy output voltage is deducted when clock voltage is also applied at frequency of 10 MHz, without any light injection.

There is another switching configuration to reduce the switching noise. The power consumed in a switched-capacitor is generally proportional to its loading. However, to minimize the power dissipation and the portion of clock signal in the capacitors C1-C4 , clock swing is reduced by keeping its low level at about 3 V. This new configuration will introduce low switching noise and lower parasitic capacitance effects. So when the clock turns off, feedthrough occurs once more as the clock goes from VB2 +VT 9 = 4.1V to 3 V. Only a portion of 1.1 V of the clock waveform couples to VB2 through C1, to VB1 through C2 and C3 , and to VD through C4 . So the perturbation of Vout is reduced considerably. Consequently, the buffer input voltage swing is increased in this configuration, hence the photoreceiver is improved resulting in a higher operating frequency.

Yet, this switching configuration does not work in our circuit, by the fact M8 and M9 are hold continually on and create a current-loop in the preamplifier. This current-loop is a source of noise. Other preamplifier designs are more useful for this switching configuration in [Kuo95].


V.7 Experimental results

The circuit proposed in Fig. V.9 was designed and fabricated in a 0.7-µm 5-V n-well CMOS technology. Fig. V.13 shows the photograph of the synchronized photoreceiver under test. Measurement with well area AB2 of 60 × 60 μm 2 and under a dark laboratory environment result in a dark-current of about 154 pA, using an hp_4145B semiconductor parameter analyzer.

The photoreceiver occupies an effective area of only 100× 60 μm2 (the output buffer and pads are not included). During the experiments, Vbias is held at 0-V, the clock swings from 0 to 5-V, and the light input was given as 5-ns pulses of 830-nm laser diodes.

Figure V.13 Photograph of the dynamic photoreceiver under test. The white spot in the bottom of the figure defines the injected input light into the enlarged base area

AB2 = 60 × 60μm 2 of Q2.

The photoreceiver’s dynamic range of optical power is as wide as 40 dB at a bit-rate of 100 Kb/s. The minimum detectable external optical energy level was 135 aJ (-45.7 dBm/beam) at this frequency, as shown in Fig. V.14. We assume a detector responsivity of 0.5 A/W by considering that 25 % of the given 830-nm laser is reflected [Ayadi97a], which means that only 423 electrons generated in the diode n-well-substrate of Q2 are required for changing the output state. This corresponds to Iph = 13.6 nA minimum photocurrent generated and Irep = 1.696 mA reflected current.

The fall time of the generated signal Vamp is ∆t = 0.56 ns which is derived from i = C dV dt( ) calculations.


0.1

1

10

100

105

106

107

108

frequency (Hz)

min

imum

inpu

t lig

ht e

nerg

y (f

J)

simulation(25MHz, 16fJ)

measurement(25MHz, 35fJ)

Figure V.14 Plotted minimum injected light energy to the photoreceiver with the injection of 830-nm laser diodes. The simulated value at 25 MHz is located close to the measured value.

40

30

20

10

0

105

106

107

108

frequency (Hz)

dyna

mic

ran

ge (

dB)

Figure V.15 Measured dynamic range of the photoreceiver with the injection of 830-nm laser diodes.

The photoreceiver performances in minimum detectable light and input dynamic range are measured and plotted in Fig. V.14 and Fig. V.15, respectively, using a package of a large cavity and 40-pins. The maximum


working frequency of the photoreceiver is achieved at 60 MHz by keeping the same configuration (Vbias , clock swing, optical pulse width). The photoreceiver introduces a 65 fJ external input light energy at 60 MHz, as depicted in Fig. V.14.

The decrease in dynamic range at high frequencies is due to the accumulation of the photoelectrons in the substrate, which escape the refreshing phase when the clock is high: the large absorption depth of about 10 µm for the given wavelength of 830-nm input laser results in a considerable sweep-out time [Sze81]. So the use of 460-nm blue laser diodes [Wu95b, Whipple98] should reduce the penetration depth by one order of magnitude and decrease the photocarrier density in the substrate [Lu96]. Thus the dynamic range should be held at about 40 dB as it is the case at low frequencies [Ayadi98b].

6

543210

5004003002001000

time (x10-9

s)

outp

ut (

V)

6

543210

optic

al in

put p

ulse

s (a

.u.)

cloc

k (V

)

Figure V.16 Given clock and optical inputs to the single-beam photoreceiver (top) and measured output voltage (bottom) at frequency of 50 MHz by injecting 5-ns pulses of 830-nm laser diodes.

Fig. V.16 shows the experimental verification of the operation of the CMOS photoreceiver at 50 MHz. A laser diode is synchronized to the clock as shown in the top panel of Fig. V.16. The optical input was given, repetitively, to the base of Q2 in the order ‘000101011111’ as shown in the top panel of Fig. V.16. ‘0’ means that no light was injected during the appropriate half clock period, and ‘1’


means that an optical input pulse of light was injected during the appropriate half clock period. The output V pad in its RZ format is shown in the bottom panel of

Fig. V.16. It can be seen that the output pattern matches the input pattern.

Higher operating frequency is also possible. An optical input of 1-ns pulses, 830-nm laser diode is used. These short laser pulses are able to generate photocurrent pulses of 5-ns [Ayadi98a]. Hence the photoreceiver is improved in a higher operating frequency. We measured 13.3 fJ external pulse energy at 100 MHz, or -18.8 dBm/beam external power. The output pattern shown in Fig. V.17 matches perfectly the repetitive string of the optical input pulses described previously.

6

5

43

21

0

28024020016012080400

time (x10-9

s)

outp

ut (

V)

Figure V.17 Improvement of 100 MHz maximum frequency of the photoreceiver by injecting 1-ns pulses of 830-nm laser diodes.

V.8 Conclusion

A new circuit design technique has been devised to enable the conversion of optical pulses to electrical digital signals. An external clock control technique is used to provide a high operating frequency. The need for any external layer or device for hybrid detection of light is eliminated through the exploitation of the local CMOS p-n junctions. An auto-reverse bias voltage is applied to the p-n junction by the clock signal to give the detector stage a high speed response and sensitivity.

With this design technique, we have succeeded in the development of a high-speed, high-sensitive CMOS photoreceiver in the inexpensive standard 0.7-µm 5-V n-well CMOS technology. The maximum frequency achieved for the


demonstrated synchronized photoreceiver is 100 MHz with only 13.3 fJ/pulse external light energy.

Our strategy for the conception of an original high-speed CMOS synchronized photoreceiver should play a significant role in the evolution of the state-of-the-art monolithic lightwave receiver, because the realization of a high-speed photoreceiver in CMOS technology offers the possibility to incorporate the sensor and the processing circuitry in a single IC. It has developed into one of the most promising photodetectors for Si-VLSI optical interconnection.

Chapter VI Technology 85

Chapter VI

Technology and Optical Fiber for Inter-chip Data Communications

VI.1 Introduction

It is reported in [Krishnamoorthy97] that by 2001, the integration density for silicon CMOS field-effect transistor logic is expected to be up to 13 million transistors and the projected on-chip clock rate to be 600 MHz. The enormous bandwidth that will be available for computation and switching on a silicon IC will create an increasing demand for high-bandwidth input and output (I/O) to a VLSI circuit. The optical interconnection should overcome this need of I/O. This will encourage the development of high-density, high-speed CMOS photoreceivers for the evolution of optoelectronic very-large-scale integrated circuits (OE-VLSI).

The operating frequency of the transistor increases when its gate-length decreases (down-scale evolution), so the 0.1 µm generation of CMOS technology is expected to be available around 2007-2010 [Krishnamoorthy96] and the operating frequency should be about 800 MHz or more. Consequently, the CMOS photoreceivers, that we have developed during our work, are expected to be operated at this range of frequency.

One particular opportunity in communication between electronic chips is that optical interconnections do not have the problem that their bit-rate capacity falls off rapidly with distance; electrical interconnections quite generally have a bit-

86 Chapter VI Technology

rate capacity that falls as the square of the length for a given cross-sectional area [Miller97]. Thus makes long, thin, high-speed electrical interconnections impractical.

Optical interconnections will allow densities of information flow much larger than the few Gbit/s/cm2 typical for connectorized coaxial cable a few meters in length. Sophisticated optical systems can handle much greater distances and bit-rates with, for example, 20 Gbit/s transmitted over 232 km of optical fiber in [Tkach95].

The most important aspects of OEIC is the capability to incorporate not only multifunction but also multichannel electronic circuits on a single chip, which will be indispensable to meet future needs for high-speed large-capacity optical communication systems. OEIC modules realized during these last years by Hitachi, IBM and other laboratories are limited to few multichannels with not more than one or two dozens of photoreceivers connected to optical fibers, see work in [Takai94, Jackson94, Ewen91, Acklin95]. This is primarily due to the difficulty of fabrication, and the simplification of the integrated structure and the packaging is the basic requirement.

Due to the complexity of fabrication, the cost of building and packaging, and the low yield of the hybridized OEIC interconnection devices [Dagenais95], we plan however to develop parallel silicon-based optoelectronic chips interconnected monolithically with more than 128 channels per chip (128 ch/chip). The model proposed in this chapter can be easily standardized to overcome the difficulty of fabrication and packaging and then decrease considerably the cost.

Our single-beam photoreceiver, which was developed in an inexpensive CMOS technology and presented in the previous chapter, will participate for the realization of the high yield OE-VLSI with 128 ch/chip. This high-speed, high-dense photoreceiver will play a significant role in cost reduction.

This chapter should not be construed as ruling out all of its contents by the fact that the hardware measurements are not totally achieved. The design should merely be considered as an artist's view. The realization of a Si-based OE-VLSI in industry with the participation of different specialists in optical fibers and packaging should involve this OEIC in the production of our day-computers with an option of high-speed optical interconnection for the long distance networks, such as the Internet with an addition of up to 12.8 Gbit/s optically instead of the presently used and insufficient 10- to 100 Mbit/s electrical interconnections. There is also a possibility for optical interconnection between


different electronic daughter-boards and the motherboard inside the computer [Kosaka97, Danzer96].

VI.2 High-density Si based optoelectronic chip

VI.2.a Strategy

It is well known that the hybridized optoelectronic devices present an overall yield of about 99.84 % [Krishnamoorthy96] which is poor, but the CMOS devices present a high-yield of around 99.9999 % (depends on the chip area). The decrease of this end by growing another material on CMOS devices for the realization of hybridized optoelectronic devices is not a great solution in our opinion, because the large number of failed devices is not acceptable in the manufacturing of integrated circuits.

To preserve the high-yield of CMOS devices, the Si chip should be protected from the aggressive process used for the realization of V-grooves, fiber connections between chips, and flip-chip bonding pads on the Si chip.

The proposed monolithic optoelectronic Si-chip designed with CMOS photoreceivers at the periphery of the chip has the potential to overcome the decrease in yield because there is no need for a special mask [Ayadi97b] and the high-yield CMOS chip is therefore protected.

VI.2.b Design

The design goal for our optoelectronic chip module in its 128 ch/chip is described below.

The module design requires standard optical interconnection to overcome the complexity in fabrication and the cost in packaging. So the photoreceivers are designed at the periphery of the chip as it is the case for the classic pads. To do this, our single-beam photoreceiver array is aligned and the n-wells of the BJT phototransistors are placed at the edge-of-die behind the pad array. The waveguide-photoreceiver is free-space connection [Goodman84, Tooley96] as depicted in Fig. VI.1.

The light is horizontally injected to the lateral sides of the chip at the level of the n-well/substrate and affects the n-well and the substrate of the BJT phototransistors of the single-beam CMOS photoreceiver [Ayadi98a], as shown in Fig. VI.1.


Si substratewaveguide

-

bot tom of the ceramic package

- 100 µm

emitter

n-well

-

e+e-e+e-

e+e-

e+e-

e+e-e+e-

e+e-

75 µm

40 µm

Figure VI.1 Lateral incoming light. The waveguides are placed in front of the active layer of the photodetector. The light affects the n-well area, the depleted layer, and part of the substrate. The gray volume defines the spatial generated photocarriers by a horizontal light injection to the 75 x 40 µm2 n-well of the p-n-p BJT phototransistor.

The packaging of the module is the most important requirement to render possible the assembly of the optoelectronic chip, so the use of the waveguides inside the ceramic package for guiding the incoming light from the external network fiber ribbons to the photoreceivers is a great solution for its low loss in light coupling. With this technique, the fiber ribbons can be handled to the optoelectronic chip, so that this external connection to the chip becomes flexible in connection and disconnection.

The horizontal injection of light to the active area of the BJT photoreceiver has the advantage that it defines approximately the affected depth of the Si-substrate. By choosing a slim waveguide and a short longitude distance between the ceramic package and the Si-substrate, a shallow Si-substrate is affected by the horizontal input light. This can perform the operating frequency and the dynamic range of the single-beam CMOS photoreceiver by reducing the diffusion time in the substrate, as detailed in the previous chapter.

It is reported in [Tsuchiya77, Young73] that the separation distance between two passive optic devices induces a loss due to the spread of the output light from the waveguides with a specific numerical aperture (around 0.6). The longitudinal misalignment loss is given by

losslong = −10 log10 ηlong (VI.1)


with ηlong is the coupling efficiency and is simplified and expressed by

ηlong ≅ 1−z2l

2 Λ( )12⎡

⎣ ⎢ ⎤

⎦ ⎥ (IV.2)

where Λ is the specific refractive index difference between core and clad of the waveguide, l is the width of the waveguide endface which is faced the Si-chip, and z is the separation distance between the waveguide and the Si-chip (longitudinal distance). z is considered to be smaller than l 2 tan ϕo , where ϕo is the maximum ray angle, emerging from the waveguide end, and is given by

ϕo =n1n0

2 Λ (IV.3)

where n1 is the waveguide core refraction index, and n0 is that of the medium between waveguide and Si-chip. The plot of the longitudinal loss is shown in Fig. VI.2. Note that this plot does not take into account other interfered phenomena as the effect of the separation environment (air in our case) which will be considered separately later.

1.00

0.75

0.50

0.25

0.00

140120100806040200

Inse

rtio

n lo

ss (

dB)

longitudinal distance (µm)

Figure VI.2 Insertion loss due to longitudinal distance between the endface of the waveguide and the lateral side of the Si-chip, after [Mossman81, Tsuchiya77].

VI.2.c Assemblage

For stable temperature coupling, all optical parts, like the waveguides, ferrule connector, and ceramic package should be built and assembled together during packaging fabrication. High precision at sub-micrometer level is required for the packaging processes, and the thermal expansion coefficients of different parts should be closely matched to avoid the misalignment under thermal shocks.


Figure VI.3 Die of the optoelectronic chip made in CMOS technology. The photoreceivers are designed at the edge of the chip. 32 photoreceivers fit at each side, meaning an addition of 128 Gbit/s optically to the classic electronic inputs.

The proposed optoelectronic module can be assembled through the following three principal advantages:

(1) the n-well potential of the p-n-p BJT phototransistor is independent of the junction area [Ayadi98a], so an extension in n-well size does not affect the performances of the photoreceiver;

(2) the waveguide is geometrically operated in shape and fan-out/fan-in [Jackson94, Kosaka97] to guide the incoming light from the external networks to the photoreceivers into the Si chip;

(3) the ceramic package is made in multilayers of size up to 100 x 100 mm in lateral dimensions to a tolerance of ± 0.5 mm [Chang96], and they can consist of up to 30 layers in the most advanced process. This should make possible the growth of waveguides at a certain ceramic level.

The main advantage of this model is that the fiber ribbon can be easily handled in connection/disconnection from the ferrule connector which is sandwiched with the ceramic package.

A new optoelectronic chip of 5 x 5 mm2 was designed and made in 0.7-µm 5-V n-well CMOS technology. The chip contains an array of 32 x 4 single-beam photodetector circuits connected together at the periphery of the chip, see Fig. VI.3. This means the design contains a parallel system of 128 ch/chip for optoelectronic interconnections, and if we remember that our single-beam photoreceiver works at 100 MHz first try [Ayadi98a] with only -18.8 dBm/beam of


830-nm input laser, an addition of 12.8 Gbit/s is optically possible in our approach.

VI.2.d Module description

The whole parallel system of 128 ch/chip needs only three electronic pads for the distribution of 5-V power supply, ground and clock synchronizer. Optical pulses come from the fiber ends to single-beam photoreceivers horizontally through the waveguides, as depicted in Fig. VI.4. These waveguides are deposed at a lower level than the existing classic metallized traces. The external connection is basically a fiber ribbon ended by a connector plug that is flexible in connection and disconnection by the use of the ferrule connector [Satake94, Nagarajan98] that is sandwiched and fixed in the ceramic package.

The build of the waveguides and traces in two different levels provides a maximum capacity of external connection to the Si chip.

ferrule connectorPGA

ceramic packagebond wires

pinsfiber ribbon of 32 fibers

external end of waveguides

Si-Chip

seal ring

w aveguid es

2.2 cm

5 cm

traces

guide-hole

guide-pinconnector plug

optical fibers

Figure VI.4 Lateral connection of optical fibers to the electronic chip. The waveguides are deposed on the PGA ceramic package at the level of the n-well/substrate of the photoreceivers in the chip. The internal metallization at a higher level ensures the electrical connection from the bonded pads to the pin-grid-array (PGA). The 4 fiber ribbons are connected at the external sides of the chip and are guided by guide-pins and fixed to the ferrule connectors. The ferrule connectors are fixed permanently during the ceramic processing. Si-chip of 5 x 5 mm2 contains a total capacity of 32 x 4 CMOS photoreceivers for achieving 128 channels.


The processes of these optic (waveguides, ferrule connectors) and electronic (traces, seal ring) connections have to be adjusted during fabrication of the ceramic package to a high precision to avoid misalignments.

During packaging processes, the ceramic package (type pin-grid-array, PGA), that is considered the best package for the next IC generation [Chang96], has the capability to bear waveguides and metallized traces at different levels [Jackson94]. The Si chip should be separated and cut from the wafer at the n-well edge of the photoreceivers which are designed at the periphery of the Si chip, and the Si chip should be glued in the lightly spaced ceramic cavity. So the dimension of the ceramic cavity should be lightly larger than Si chip by about 100-µm at each side to optimize the loss in light by keeping the waveguides close to the BJT phototransistors. This free space between the two lateral edges of the Si-chip and the ceramic cavity is good enough to protect the Si-chip from the thermal stress that can be fatal to it by inducing chip cracking [Chang96].

VI.2.e Alignment

It is important to interconnect two passive optical devices, such as in our module optical fibers, to waveguides. The requirements for the coupling fibers to waveguides and waveguides to Si-chip are: 1) high performance with the minimum of light loss; 2) an easy assembly process; and 3) cost effectiveness.

There are two methods for the coupling. One is active alignment, and the other is passive alignment. With the active alignment the devices are aligned using a precision-machine and the connection ports are fixed using adhesive with high alignment accuracy of less than 1.0 µm and good stability in term of a high temperature variation [-40 ºC, 85 ºC] and a high humidity at 70 ºC and 90 ºC, an average loss variation was observed at 0.15 dB in [Yamada92].

The passive alignment needs V-grooves and guide- pins and holes. These V-grooves and guide-pins and guide-holes must be formed and processed based on the position of the markers [Kihara95] and ensure the self alignment of the passive optical devices, with an accuracy of 1.3 µm and an average loss variation of 0.2 dB in a temperature range of [-25 ºC, 70 ºC]. These performances were observed in [Kihara95].

In the active alignment, the devices are fixed permanently, while in the passive alignment, the devices are flexible in connection and disconnection. There is a need in our module to the two different categories of alignment. The active alignment can be used for the alignment of waveguides and die, while the passive alignment should be used for fibers and waveguides alignment.


When the die is separated from the wafer, a silver filled epoxy adhesive is applied to the package substrate at die attach. Die is picked from the wafer and placed robotically on the adhesive. The die is connected to the gold plated package leads by way of gold wedge wire bond technology. Bond pad and package lead placement accuracy and wire pull strength monitors ensure high integrity connections, see Fig. VI.5.

Die

pin

Die attach plane (GND)

Silver filled epoxy

dielectric layertrace layers (signals, power) bonding wire

heat spreading (PWD)heat spreading (GND) thermal via optional heat sink

waveguide layer

ceramic substrate

Figure VI.5 Cross section of a typical CPGA piece part. The Si-chip (die) is positioned in the ceramic cavity and fixed by an epoxy. The waveguide layer faces the lateral Si-chip at a distance of about 100 µm for a free space coupling with low loss. The trace, waveguide, and dielectric layers have a high transition temperature. The vias conduct heat away from the die to a heat sink or pipe that is connected to a fan (not in the drawing) to stabilize the temperature at 40 to 45 ºC. The prototype is based on the developed and proposed package of our day-processor Pentium by Intel®.

Each waveguide grown in the ceramic package should match the lateral n-well area of 40 x 2.2 µm2 of the corresponding photodetector. The waveguides in fan-out take more larger sizes at the external side of the ceramic package, for example, 20 x 5 µm2 faced the Si-chip, and 70 x 70 µm2 faced the optical fiber of 50 x 50 µm2 core to minimize the lateral misalignment loss in light coupling.

The external network optical fiber ribbon, of about 5 cm width, should be attached to the optical waveguides by a precision ferrule connector [Jackson94, Senior92]. This ferrule connector is sandwiched to each external side of the ceramic package of about 5 cm too, based on the dimensions of our-day processor package. The alignment of the optical fiber and the optical waveguide endfaces is ensured by the guide-pins of the connector plug and their


corresponding guide-holes [Kajita97] of the ferrule connector, as shown in Fig. VI.4. The fiber ribbon and the ferrule connector are now in industrial use [MTTM ferrules].

VI.3 Special considerations and performances

VI.3.a Design considerations

We have used only 100 µm depth from the chip edges for the design of the photoreceiver array. The classic pads are kept behind the photoreceivers and inside the chip, as shown in Fig. VI.3. Optical pulses coming from the fiber end have the capability to affect the n-well and substrate layers of the photodetector horizontally.

10.0

7.5

5.0

2.5

0.0

800070006000500040003000200010000

aver

age

inje

cted

ligh

t pow

er (

µW)

n-well area (µm2)

Figure VI.6 Measurement and confirmation that our detector area (n-well) is independent of the injected light power. The average injected 830-nm laser is about 7 µW for the different exposed n-well areas at the frequency of 50 MHz. This power is necessary to trigger the BJT phototransistor.

An extension in n-well area of the BJT phototransistor of our single-mode photoreceiver [Ayadi98a] does not change its potential, because the increase in the junction area induces more generated electrons under light injection, yet, they accumulate in the n-well volume that is also larger by the same factor as the junction. Thus there is no remarkable change in charge in the n-well for a larger exposed area, this independence was confirmed experimentally and plotted in Fig. VI.6.

We have measured different n-well areas (from 20 x 20 µm2 to 80 x 80 µm2). The average injected power necessary to generate the needed quantity of photocarriers is the same for the different exposed areas at about 7 µW at a


frequency of 50 MHz. This injected power is needed to trigger the p-n-p BJT phototransistor, see Fig. VI.6.

This characteristic is exploited in the design of the optoelectronic Si-chip. The design of a 40 x 75 µm2 n-well of the BJT phototransistor is enough for the stretching of the n-well until the edge of the Si-chip, as depicted by an arrow in Fig. VI.7.

Figure VI.7 The independence of the n-well potential to the junction area makes the extension of the photodetector n-well area to the Si-chip edge practical. The pads used for electrical connections are designed inside the chip at about 120 µm from the edge.

It is important to remind the designer that in most of CMOS technology, the design rules oblige us to leave an empty space, known as scribe lane, of about 120 µm from the pads to the edge-of-die, in order not to damage the pad structure during dicing and not to cause the undesirable stress concentration on the pad during bond-wiring which may lead chip cracking. We have used this scribe to design the photoreceivers array, as shown in Fig. VI.7.

As preparation for the die attachment, the wafer is mounted on a pressure sensitive carrier tape and diced with a high speed saw with an accuracy of better than 2 µm [Kihara95]. The cut should occur in a straight line and is expected at a distance of about 5 µm from the n-well array of the BJT photoreceivers to protect the n-well structure, as shown in Fig. VI.7. The cut wafer is washed with a detergent solution to remove silicon duct. The lateral side of the die should be planarized by a uniform polisher [Chang96].

It is demonstrated in the last chapter that when the clock is applied, the depletion layer n-well/substrate is about 2 µm. The required time for the generated photoelectrons between the die-cut (die edge) and the n-well array to reach the n-wells depends on the distance between the depletion layer and the


die-cut. According to the theory, this diffusion time is given by τi = Li2 Di , (i=n,

p), and plotted in Fig. VI.8.

Figure VI.8 The photoelectrons that are generated in the substrate by the injection of light to the Si-chip horizontally diffuse to the n-well of the BJT phototransistor. The diffusion time for this event depends with the distance between the edge and the n-well. The insert: zoom of the small distances.

VI.3.b Waveguide processes

The glass waveguides can be processed on the ceramic package by using flame-hydrolysis deposition and reactive ion etching [Miyashita88]. A porous glass soot consisting of two layers, a cladding with lower refractive index and a core with higher refractive index, is deposited on the ceramic substrate at the level of the active zones of the silicon chip. The porous layers are then consolidated together at temperatures of about 1200 - 1400 ºC to densify the material into a smooth glass planar waveguide film.

To form three-dimensional waveguides, the film is patterned using reactive ion etching techniques. It is demonstrated in [Jackson94] the realization of waveguides with thicknesses of the cladding and the core layers of 44 and 36 µm ± 2 %, respectively, which correspond to a total glass thickness of 80 µm ± 1.6 µm.

The core width of the waveguide should be made larger on the outside than on the inside of the ceramic package so as to lower coupling loss at the connector [Kosaka97, Jackson94].


VI.3.c Multi-fiber connector

The ferrule connector is commercially available [Senior92]. The alignment to the waveguides can be done by guide-pins. These guide-pins should be positioned and fixed permanently into the corresponding opened holes in the ceramic upon the waveguide are formed, thus allowing photolithography alignment of the Ferrule connector to the optical waveguides in the horizontal and vertical directions with high precision.

The optical fiber ribbon will mate directly with the ferrule connector and hooked with precision guide-pins, coil springs, and slit sleeve. With this technique, each optical fiber faces the corresponding waveguide with a precision of better than ± 2 µm [Kihara95]. AT&T and others have developed multiple fiber connectors of about 10 channels with a typical insertion loss of only 0.6 dB, see [Ota87, Sakake88]

VI.3.d Loss in light propagation

The advantage of using waveguides is the low loss that is observed at 0.3 dB/cm for the waveguide width of 55 µm at a wavelength of 850 µm [Jackson94]. This propagation loss is most likely due to the surface roughness of the ceramic substrate. By considering that the waveguide does not access the distance of 2 cm in the proposed module, the propagation loss is taken at 0.6 dB. An addition to this, the loss of waveguide S bends and radii S bends [Jackson94] is about 0.4 dB/cm, meaning 0.8 dB of loss.

The optical connection from the waveguide to the external optical fiber contributes an addition loss of 0.4 dB in [Jackson94]. At the other end of the waveguide and adding to the 0.8 dB due to the 100 µm longitude between waveguide and Si-chip (Fig. VI.2), a loss of 0.36 dB occurs due to the Fresnel reflections at waveguide-air and air-silicon [Senior92] according to the theory given by the equation

lossFres = −10 log10(1− r ) (IV.4)

where r is the fraction of light reflected at a single interface and expressed by

r =n1− n0n1+ n0

⎛

⎝ ⎜

⎞

⎠ ⎟

2

(IV.5)

where n1 is the refractive index of the waveguide or silicon and n0 is the air

index.


A total loss of the module including photoreceiver/ waveguide/ ferrule-connector/ fiber-ribbon is estimated for the proposed module at 2.96 dB, and observed in other developed modules at about 2.8 dB by IBM in [Jackson94] and 3 dB by NEC in [Kosaka97]. It is also reasonable to see the high loss measured in some applications at about 9.7 dB by Fujitsu in [Nakagawa95], due to displacement from the specific position, misalignments of optical fibers and particularly the angular misalignment which can cause significant attenuation. Careful design, assemblage, and processes are the guarantee for the low loss in optical coupling.

VI.4 Conclusion

An extension to the low-cost OEIC receiver in an inexpensive CMOS technology, OEIC ceramic packaging is being explored for use in optically interconnected computers, which today involve robotically aligned and assembled precision-machined components.

The structure of the future optoelectronic ceramic packages that we expect should contain the following:

1/ Waveguides, which are used for the connection between photoreceivers in the chip and the external optical fibers, are formed in the ceramic package at the n-well/substrate level of the CMOS chip.

2/ Traces, which are used for the connection of pads in the chip to the external pins, are formed at higher levels than the waveguide level.

3/ Four ferrule connectors, which are used for the connection of the external four 32-fiber ribbons to the waveguides, are sandwiched with the four-side of the ceramic package.

4/ A defined ceramic cavity, in which the Si-chip is glued, is slightly larger of about 100 µm than the Si-chip dimensions.

The connection of the fiber ribbons to the optoelectronic chip can be easily handled in the proposed module. The fiber ribbons coupled to the ferrule connector can be guided and hooked by two pins. The core width of the waveguide should be made larger on the outside than on the inside of the ceramic package so as to lower coupling loss at the junction. We expect a total loss of about 2.96 dB in light coupling.

We propose with this module an additional 128 optical fibers connected to the Si-chip by using the detailed techniques, meaning an additional of 12.8


Gbit/s optically to the classic electronic capacity. The actual operating frequency of 100 MHz of our single-beam photoreceiver can be multiplied two or three times by a careful design, by a more progress CMOS technology, and by the injection of other wavelengths. The model can easily be standardized to overcome the complexity and the cost.


Chapter VII Conclusions 101

Chapter VII

Conclusions

We have realized an ultra-sensitive III-V/Si hybridized photoreceiver. The maximum frequency achieved for the proposed receiver is 50 MHz and requires only 3 fJ. Flip-chip technique is therefore required to prove higher operational frequency above the 500 MHz. So this technique is complicated and expensive.

A new design technique has been devised to enable the conversion of optical pulses to electrical digital signals. The need of any external layer or device for hybrid detection of light is eliminated through the exploiting of local CMOS p-n junction. With this design technique, we have succeeded in developing a full CMOS optical receiver with a wide dynamic range and very high sensitivity using standard 0.7-µm 5-V n-well CMOS technology. Double-beam and single-beam monolithic CMOS photoreceivers have been developed and demonstrated at high frequency above the 100 MHz and size below 100 x 100 µm2. The double-beam photoreceiver works at 180 MHz with 176 fJ external energy and has a potential use in holographic memories. The maximum frequency achieved for the demonstrated single-beam photoreceiver is 100 MHz with only 13.3 fJ external light energy. This new single-beam dynamic photoreceiver can be easily suitable for Si OEIC photoreceiver, because of its small area, its high operating frequency and its simplicity for conversion of single-optical pulses to

102 Chapter VII Conclusions

logical-electronic signals. We believe the introducing of the idea of exploiting Si photodiode dynamically by applying an external clock will be very useful in Si OEIC receiver.

Operating at high frequency, our monolithic silicon photoreceiver appears very attractive for its potential for cost savings and size reduction compared with hybrid receivers. This indicates the possibility of introducing full silicon photoreceiver OEICs in optical interconnections at the interchip level without delay time problems. So this successful work can be extended to the realization of an optoelectronic photoreceiver system for parallel optical interconnections. An additional 128 single-beam photoreceivers per chip of 5 x 5 cm2 is designed and fabricated in 0.7-µm 5-V n-well CMOS technology. The techniques for achieving 128 channels are detailed and the possibility of incorporating ceramic package for the future optoelectronic package is discussed.

This first stage allows an additional of 12.8 Gbit/s/chip optically to the classic electronic I/O pads. These optical interconnections should be exploited for long distance and at high frequency interconnections for OE-VLSI by using optical fibers and waveguides.

Appendices 103

Appendices

Appendices

A.1 Appendices 1

**Simulation of the comparator amplifier. Frequency = 1 GHz** * Typical Models CMOS-MIETEC 0.7 µm date 1995 * Written by Ayadi Kamel (PhD. C. IMEC-VUB) * ND & PHD Models: based on a limited number of measurements .model n nmos +level=3 tox=170e-10 xj=.1e-6 nfs=1.2e+11 vto=.75 nsub=7e+16 + delta=.85 uo=470 theta=.08 rsh=520 eta=.0052 delw=0 ld=.1e-6 +vmax=1.94e+5 dell=.2e-6 wd=.05e-6 kappa=1.0e-3 js=1e-3 nlev=0.0 + lis=2 istmp=10 cj=5.0e-4 mj=.32 cjsw=2.8e-10 mjsw=.23 pb=.68 + fc=.5 cgso=3.1e-10 cgdo=3.1e-10 kf=3e-28 af=1 xl=.2e-6 xw=0e-6 .model p pmos +level=3 tox=170e-10 xj=.05e-6 nfs=.5e+11 vto=-.95 nsub=3.5e+16 + delta=.8 uo=158 theta=.135 rsh=870 eta=.03 delw=0 ld=.06e-6 +vmax=7.2e+5 dell=.15e-6 wd=.1e-6 kappa=1.0e-3 js=1e-3 nlev=0.0 + lis=2 istmp=10 cj=6e-4 mj=.51 cjsw=3.6e-10 mjsw=.35 pb=.9 + fc=.5 cgso=2.2e-10 cgdo=2.2e-10 kf=5e-30 af=1 xl=.15e-6 xw=0e-6 .options post

104 Appendices

m1 4 6 0 0 n w=200u l=0.7u m2 2 7 0 0 n w=200u l=0.7u m3 4 6 5 1 p w=350u l=0.7u m4 2 7 3 1 p w=350u l=0.7u m5 5 3 1 1 p w=10u l=0.7u m6 3 3 1 1 p w=10u l=0.7u m7 3 4 1 1 p w=250u l=0.7u m8 5 2 1 1 p w=250u l=0.7u m9 4 2 0 0 n w=100u l=0.7u m10 2 4 0 0 n w=100u l=0.7u m11 8 4 1 1 p w=350u l=0.7u m12 11 2 1 1 p w=350u l=0.7u m13 9 10 8 1 p w=350u l=0.7u m14 10 9 11 1 p w=350u l=0.7u m15 9 4 0 0 n w=150u l=0.7u m16 10 2 0 0 n w=150u l=0.7u m17 9 10 0 0 n w=150u l=0.7u m18 10 9 0 0 n w=150u l=0.7u c1 10 0 1p *load capacitance at left side c2 9 0 1p *load capacitance at right side vdd 1 0 5v *input voltages at left side, frequency of 1 GHz r3 36 6 .01k v1 36 0 pwl(0 3.5 .34n 3.5 .37n 1.4 .67n 1.4 .7n -4 .8n -4 + .9n 0 1n 0 1.03n 3.5 1.33n 3.5 1.36n 1.55 1.66n 1.55 1.69n -4 + 1.79n -4 1.89n 0 2n 0 2.03n 3.5 2.33n 3.5 2.36n 1.4 2.66n + 1.4 2.69n -4 2.79n -4 2.89n 0 3n 0 3.03n 3.5 3.33n 3.5 3.36n 1.55 + 3.66n 1.55 3.69n -4 3.79n -4 3.89n 0 4n 0 4.03n 3.5 4.33n 3.5 + 4.36n 1.4 4.66n 1.4 4.69n -4 4.79n -4 4.89n 0 5n 0) *input voltages at right side, frequency of 1 GHz r4 37 7 .01k v2 37 0 pwl(0 3.5 .34n 3.5 .37n 1.55 .67n 1.55 .7n -4 .8n -4 + .9n 0 1n 0 1.03n 3.5 1.33n 3.5 1.36n 1.4 1.66n 1.4 1.69n -4 + 1.79n -4 1.89n 0 2n 0 2.03n 3.5 2.33n 3.5 2.36n 1.55 2.66n 1.55 + 2.69n -4 2.79n -4 2.89n 0 3n 0 3.03n 3.5 3.33n 3.5 3.36n 1.4 + 3.66n 1.4 3.69n -4 3.79n -4 3.89n 0 4n 0 4.03n 3.5 4.33n 3.5 + 4.36n 1.55 4.66n 1.55 4.69n -4 4.79n -4 4.89n 0 5n 0) .print tran v(6) v(7) v(10) v(9) .tran .005n 6n .ic v(10)=0 v(9)=5 .plot tran inSi-L=v(6)

Appendices 105

.plot tran inSi-R=v(7)

.plot tran outSi-L=v(10)

.plot tran outSi-R=v(9)

.measure tot_power avg power goal=100mw

.print power

.end

106 Appendices

A.2 Appendices 2

A.2.1 Principal operation of CBLSA

The schematic circuit of the CBLSA is shown in Fig. A.1. The external drive circuitry for writing operations is symbolized by two ideal current sources of pulses I1 and I2 and they may be the complementary current output from the two sides of a single cell. The bit-line capacitances are represented by Cbl. M5 and

M6 are biased in the linear region and provide a low-impedance clamp between the bit lines and the sense-amplifier potential Vref. This reference is a low

potential used to set the precharge voltage for the bit lines. It can be as low as the ground for the circuit or as high as approximately 1/3 Vdd.

Figure A.1 Schematic of the clamped bit-line sense-amplifier CBLSA sense-amplifier [Blalock91].

To make a comparison between our CSA and this CBLSA, Vref is grounded.

The geometric dimensions W/L of the sense-amplifier are unchanged for both circuits. External capacitances of about 100 fF are added to the two output nodes (out+, out-) of the CBLSA. These capacitances are basically the input capacitances of the additional buffers which are needed to drive the bit lines to the appropriate levels.

The operating of the sense-amplifier is as follows:

Appendices 107

To begin a memory access, transistor M9 is turned on, providing power to the sense-amplifier. During precharge phase, see Fig. A.2, transistors M7 and M8 are on forcing the bit lines to equal potentials at a value of 90 mV and the outputs to 1.9 V in this design. These voltages are mostly determined by the W/L ratios of M1-M4. If a difference between the left and the right input currents occur, ∆I will flow through M7 during the precharge phase.

At the end of the precharge phase, M7 and M8 are turned off and M9 is still on, M1-M4 act as a high-gain positive feedback amplifier. In consequence, the impedance looking into the source terminal of either M1 or M2 is a negative resistance, which causes M1 and M2 to begin sourcing a portion of the difference current ∆I.

Precharge phas e:

Sensing phase:

ΔI :

Figure A.2 Timing diagram with the different phases and the given difference current ∆I.

The difference current flowing through M1 and M2 flows through the small equivalent capacitance at the drains of M1 and M2, giving rise to a ∆V across the output nodes of the sense amplifier. The resulting differential voltage at (out+, out-) is rapidly amplified by the positive feedback of the sense-amplifier toward the stable state. If ∆I > 0, Vout+ is driving high and Vout- low. At the end

of the sensing, M9 is returned off. So the sensing phase is achieved and the internal power is saved.

A.2.2 Small-signal analysis

The small-signal equivalent circuit for the CBLSA is shown in Fig. A.3. Cs is now the equivalent value of Cbl and Cd of the clamped transistor M5 or M6, so Cs ≅ Cbl . Since clamped transistors are biased heavily into the linear region of operation, their output conductance gds are quite high than gm of M1 and M2.

108 Appendices

Cs

V3gmn

.(V2-V4)

1/ gds

Rd

gmp.V2

Cd

V1

Cs

gmn.(V1-V3)

V4 V2

1/ gds gmp.V1

Rd Cd

Figure A.3 Small-signal equivalent circuit of the clamped bit-line sense-amplifier CBLSA.

The large bit-line capacitance is now connected to the source of M1 (for left side) and M2 (for right side) and produces a pole and zero in the small-signal gain of each of the inverters (M1-M3) and (M2-M4) [Blalock91]. The loop gain of this configuration is expressed as

T =′ g m ′ R d 1+ s Cbl

gds

⎛

⎝ ⎜

⎞

⎠ ⎟

1+ sCbl

gmn + gds

⎛

⎝ ⎜

⎞

⎠ ⎟ 1+ s ′ R d Cd( )

⎡

⎣

⎢ ⎢ ⎢ ⎢

⎤

⎦

⎥ ⎥ ⎥ ⎥

2

(d.1)

with

′ g m = gmp +gmn

1+gmngds

⎛

⎝ ⎜

⎞

⎠ ⎟

(d.2)

and

′ R d = gdsp +gdsn

1+gmngds

⎛

⎝ ⎜

⎞

⎠ ⎟

⎡

⎣

⎢ ⎢ ⎢ ⎢

⎤

⎦

⎥ ⎥ ⎥ ⎥

−1

(d.3)

The GBW product is given by

GBW =′ g m ′ R dCd( ) (d.4)

As a result, the circuit should exhibit a response time that is independence of bit-line capacitance. This is one of the advantages of the CBLSA.

M1-M6 have a W/L = 8/0.7. M9 and M7-M8 have a W/L = 15/0.7 and 12/0.7, respectively.

Appendices 109

Using Hspice simulator, the poles at the output nodes (out-, out+) of the CBLSA are located at a frequency of 6.3 MHz, and the GBW product of this circuit is 1.3 GHz, as shown in Fig. IV.7.

The ratio of GBW products of this CBLSA and our CSA is given by

GBWCBLSA GBWCSA = ′ g m ′ R d gm Rd( ) Cbl Cd( ) (d.5)

As a result a half order of magnitude between the response time of the CBLSA and our CSA should occur.

5.0

4.0

3.0

2.0

1.0

0.0

volta

ges

(V)

7.26.86.46.05.65.24.84.44.03.63.22.8

time (x10-9

s)

Vout+

Vout-

Vd

Vpre Cbl = 0.6 pF Cbl = 1.2 pF

Figure A.4 Time response of the CBLSA for both cases: when it is loaded by an input Cbl = 0.6 pF and 1.2 pF, and generates 1-V in 1.24 ns as it is depicted by the voltage difference signals. The speed response is not affected by the input bit-line capacitances in this circuit.

The Hspice simulation of the CBLSA time response is plotted in Fig. A4. by using device parameters in table IV.1. In this simulation the Cbl is given to be

equal to 0.6 pF and 1.2 pF. The extension to 1.2 pF does not affect the speed response of the CBLSA. This improves the small-signal analysis discussed above. In Fig. A.4, the voltage difference Vd between the voltages (Vout+, Vout-)

at the output nodes of the sense-amplifier shows that the CBLSA takes only 1.24 ns for both Cbl values. This improves that the advantage of using CBLSA circuit resides in the response time independence of bit-line capacitance Cbl as

it is explained in the small signal analysis above.

As it is reported in several papers on the sense-amplifiers study, the time response formed by a cross-coupled CMOS inverter pair is directly related to the

110 Appendices

ac small-signal gain-bandwidth (GBW). So, by maximizing the GBW product, the response speed of the sense-amplifier is maximized.

References 111

References

References

A [Acklin95] B. Acklin, J. Bellermann, M. Schienle, L. Stoll, M. Honsberg, and G.

Müler, “Self-Aligned Packaging of an Optical Switch Array with Integrated Tapers,” IEEE J. Lightwave Technology, vol. 7, no. 4, pp. 406-408, April 1995.

[Ayadi97a] K. Ayadi, M. Kuijk, P. Heremans, G. Bickel, G. Borghs, and Roger Vounckx, “A Monolithic Optoelectronic Receiver in Standard 0.7-µm CMOS Operating at 180 MHz and 176-fJ Light Input Energy,” IEEE Photon. Technol. Lett., vol. 9, no. 1,pp. 88-90, January 1997.

[Ayadi97b] K. Ayadi, P. Heremans, M. Kuijk, C. D. Tandt, G. Borghs, and R. Vounckx: “A 180 MHz Standard CMOS Silicon Optoelectronic Receiver,” IEEE Circuits & Devices, vol. 13, no 1, pp. 26-28, January 1997.

[Ayadi97c] K. Ayadi, G. Bickel, M. Kuijk, P. Heremans, G. Borghs, and Roger Vounckx, “A Hybridized Optical Thyristor-CMOS Receiver for Optoelectronic Application,” IEEE Photon. Technol. Lett., vol. 9, no. 5, pp. 669-671, May 1997.

[Ayadi97d] K. Ayadi, P. Heremans, M. Kuijk, C. D. Tandt, G. Borghs, and R. Vounckx, “Combining a GaAs Thyristor - Based Optical Receiver with a 1-GHz CMOS Comparator Amplifier to Overcome Signal Delays,” IEEE Circuits & Devices, vol. 13, no 4, pp. 24-29, July 1997.

[Ayadi98a] K. Ayadi, E. F. Dirkx, and J. M. J. Sevenhans, “High-Speed, High-Sensitive OEIC Using Clocked Vertical BJTs PhotoDarlington in CMOS Technology,” accepted paper (under ref. M6065), IEEE J. Solid-State Circuits, May. 1998.

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Index 119

Index

A Absorption coefficient 32, 47, 65 Absorption depth 2, 31, 33, 35, 47, 56, 82 Accumulation 42, 82 Active alignment 92 Adhesive 92, 93 Amplification stage 9 Analog signal 6, 62 Anomaly 113, 51 Artist 86 Assembly 88, 92 Attenuate 1, 44, 77 B Bandgap 21 Base current 74, 76, 77 Base-collector 63, 64, 73, 75, 77, 78 BDJ device 28 BDJ structure 27 Beam splitter 16 Bit-error 39, 40 Bit-line capacitance 52, 53, 54, 106, 108, 109 Bit-rate 80, 85, 86 BJT 24, 25, 30, 39, 62, 63, 87, 88, 94, 95 BJT mode 30 BJT phototransistor 87, 92, 94, 96 BJT-CMOS 36 BJT-CMOS structure 36 BJT-CMOS transistor 30 blue laser diodes 82 body-effect 23, 25, 30 bond-wires 17 bonding pad 87 Boolean 7, 16 buffer 14, 15, 55, 59, 62, 75, 76, 79, 80 buried depletion-layer 39 buried p-n junctions 27

C Cascade 70 CBLSA 54, 55, 103, 104, 105, 106 CCD camera 20 Ceramic cavity 91, 92, 97 Ceramic package 87, 88, 89, 90, 91, 92, 93, 95, 97, 98, 100 Channel capacitance 75 Chip cracking 91 Cladding 95 Class-A 65 Classic pad 86, 93 Clock driver 12, 20 Clock feedthrough 75, 77 Clock rate 84 Clock transition 73, 76 Clocked photoDarlington 63, 73 Clock transition 74, 75, 77 Clocked photoDarlington 63, 73 CMOS 25, 48 CMOS comparator amplifier 6, 7, 8, 9, 14, 16, 17 CMOS photodetector 3, 39 CMOS sensor 34 CMOS technology 9 Coil spring 97 Color detection 27 Common collector 30, 64, 71 Common-mode 8 Common-mode range 8 Comparator amplifier 14 Connection/disconnection 90 Connector plug 91, 93 Conventional .i.sense-amplifier 48 Core 78, 96, 98 Coupling capacitances 76 Coupling loss 96, 98 CSA 48, 50, 52, 53, 54, 55, 106, 109 Current 23 Current feedback 11 Current mirror 9

120 Index

Current-feedback loop 12 Current-mirror comparator 65, 72 Cuts off 10 D Dark current 21 Darlington 63, 70, 71, 73, 77 Daughter-boards 87 Demultiplexer 27 Depletion edges 64 Depletion region 22, 64, 65 Depletion width 33 Depletion-layer 36, 39, 64 Detector 6, 21, 47, 49, 59, 62, 80, 83, 94 Differential topology 8 Diffusion capacitance 52 Diffusion time 31, 33, 34, 35, 38, 39, 43, 88, 96 DIME 35, 36, 37 Doping 34 Double-beam photoreceiver 101 Dynamic operation 37, 62 Dynamic range 3, 39, 80, 81, 82, 88, 101 E Edge-of-die 87, 95 Electric field 20, 22, 23, 24, 30, 36, 39, 40, 64 Electrical noise 78 Electron-hole pairs 20, 21, 22, 24, 30 Emitter 2, 5, 6, 16, 30, 63, 64, 65, 71, 74, 76, 77 Energy-band 23 Erroneous pulse 42 Excess photocarrier density 42 F Fan-in 90 Fan-out 90, 93 Feed-forward 70 Feedthrough 79 Feedthrough current 76, 78 Feedthrough noise 78 Ferrule connector 89, 90, 91, 92, 93, 94, 97, 98 FET 66 Fiber ribbon 88, 90, 91, 93, 94, 97, 98 Flame-hydrolysis deposition 96

Flip-chip 2, 17, 53, 87 Flip-flop 59 Forbidden gap 20 Fresnel reflection 97 G GaAs 2, 4, 14, 15, 19, 36, 47 GaAs-AlGaAs material 8 Gain-bandwidth 52 Gate-to-drain capacitance 75 GBW 53, 54, 110 Guide-holes 92, 94 Guide-pins 91, 92, 93, 97 H Haynes-Shockley experiment 42 High-yield 87 Hole-electron 31 Holographic memories 101 Horizontal diffusion 44 Hspice simulation 64, 74, 109 Humidity 92 Hybridized optoelectronic 87 Hybridized photoreceiver 6, 101 Hysteresis loop 13 I i-layer 32 I/O 85 I/O pad 102 IC 85 Illumination 43 InP 2, 19 Interaction 44 ISAAC 67, 70, 71 J Junction 64 L Laboratory 80 Large cavity 14 Large-signal 14 Laser diodes 14 Laserpulses 44 LATCH phase 59 Latch-up 25, 27, 30 Lateral edge 92 Lateral side 87, 95 Lens reflections 16 Lifetime 44 Light absorption 31

Index 121

Light coupling 88, 93, 98 Lightpulse 36, 39 Lightwave 84 Longitudinal misalignment 88 Loop gain 52 Loss 98 Lower edge 33 M Miller capacitance 52 Misalignment 92 Mismatch 14, 50 Modulation 32, 53, 73 Molecular Beam Epitaxy 8 Monolithic 84 Monolithic photoreceiver 3, 47 MOSFET 23, 26, 27, 50 Motherboard 87 Multi-wavelength optical fiber 27 Multichannel 86 Multifunction 86 N N+ layer 24 N+/Psub 23 n-MOSFET 48 n-well CMOS 23 n-well edge 92 n-well/P+ junction 23 n-well/substrate depletion layer 33, 65, 73 n-well/substrate depletion region 33 Near-infrared 20 Negative feedback 14 Network 86, 88, 90, 93 Neutrality 43 NMOS latch 57 Noise 14 NRZ 9, 16 Numerical analysis 70, 71 O OE-VLSI 85, 86, 102 OEIC 2, 3, 47, 86, 98, 102 Off-state 6 On-state 6 Open-circuit 21 Open-loop 67, 69, 70, 71 Optical coupling 98 Optical energy 80 Optical fiber 25, 78, 86, 91, 92, 93, 97, 98, 99, 102

Optical power 80 Optoelectronic 17 Optoelectronic chip 4, 86, 87, 88, 90, 98 Optoelectronic module 90 Oscilloscope 36, 37 Overlap capacitance 75, 76 P P+ diffusion layer 24, 30 P+/n-well depletion layer 33 P+/n-well/P- 30 P+/n-well/Psub 30 p-channel MOSFET 23 p-i-n photodiode 32 p-MOSFET 48 p-n-p bipolar junction transistor 30 p-n-p bipolar transistor 30, 63 p-n-p BJT phototransistor 25, 88, 90, 95 P-substrate 25 p-type substrate 36 Package 14, 81 Parallel system 90, 91 Parasitic capacitance 2, 52, 75, 76, 78, 79 Passive alignment 92 PD 62 Periphery 87, 90, 92 Perturbation 44, 79 PGA 91, 92, 93 Photocarrier 36 Photocarriers 35 Photocurrent 21, 23, 38, 39, 80 PhotoDarlington 63, 66 Photodetector 39, 43 Photodiode 21, 23, 34, 35, 36, 39 Photoeffect 23, 30 Photoelectron 64 Photogeneration 41 Photolithography 97 Photon 20 Photon flux 65 Photoreceiver 25, 35, 44, 77, 79 Pinch off 11, 12 Pins 14, 81, 92, 98 PMOS detector 59 PMOS version 58, 59 Pole-zeros 67, 71 Porous glass soot 96 Positive feedback 10, 14 Positive feedback loop 9, 11

122 Index

Post-amplifier 62, 65, 66, 67, 69, 70, 71 Power dissipated 77 Power injected 73 Preamplifier 62, 63, 64, 67, 79 Precision-machine 92 Precision-machined 98 Probe 37 Process 87 Processor package 93 Propagation delay 77 Pull-down 50 Pull-up 50, 51, 73 Pulsewidth 37, 39 Q Quantum efficiency 23, 33, 47, 59, 65 R R-S flip-flop 9, 10 Radiant flux 21 Radiation 21 Radii S bend 97 RAM 47, 54 Reactive ion etching 96 Read-out 36, 38, 40 Receiver 5, 6, 16, 17, 48, 54, 59, 84, 98, 101, 102 Reflection spectrum 29 Refractive index 89, 96, 97 Refresh 43, 82 Refresh circuit 36, 78 Repetitive train 39, 40, 42 RESET 49 Reset-phase 7 Responsivity 23, 65, 80 Reverse-bias 23, 39, 64, 65 Robotic 93, 98 RS flip-flop 17 RST 49 RZ 38, 39, 83 S S bend 97 Saturation drift velocity 34 Scribe lane 95 Seal ring 92 Sense-amplifier 48, 49, 50, 51, 52, 53, 54, 55, 106, 107, 108, 109, 110 Sensitivity 11, 52

Setup 16, 36, 49 Si chip 90, 91 Si OEIC photoreceiver 2, 101 Si-substrate 88 Silicon duct 95 Single poly double metals 9 Single-beam 4, 87, 88, 90 Single-beam photoreceiver 61, 82, 86, 91, 99, 101, 102 Slit sleeve 97 Small-signal analysis 71 Smooth glass 96 Special mask 32, 47, 87 State-of-the-art 84 Steady state 41 Stevenson-Keyes method 40 Stretching 95 Substrate/n-well diode 25 Sunlight 36 Surface passivation 29 Surface reflectivity 65 Sweep-out time 47, 82 Switch-on 7 Switched-capacitor 79 Switched-gate noise 78 Symmetric 50, 52 Synchronized photoreceiver 61, 72, 80, 84 T Temperature 14 Temperature range 92 Thermal shock 89 Thyristor pair 6, 7, 8, 17 Top-down 50 Traces 91, 92 Transconductance 23, 52 Transconductance parameters 14 Transimpedance 70, 71 Transistor action 65, 76, 77 Transit time 34 Trigger 7, 16, 39, 48, 49, 65, 94, 95 Triode regime 9, 10, 77 U Upper edge 22, 33 V V-groove 87, 92 Vertical p-n-p BJT 63VLSI 1, 2, 3, 5, 84, 85

Index 123

W Waveguide 4, 88, 89, 90, 91, 92, 93, 96, 97, 98, 102 Wavelength 23 Wirebonding 14, 15 Y Yield 2, 5, 26, 47, 67, 86, 87

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High Speed CMOS Photoreceivers and Technology for … · 2011. 3. 19. · Kamel AYADI . V E R S N I...

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